Multi-Level Memory Cell Grouping for Data Density
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Solution Overview
Problem
Current memory devices face challenges in efficiently storing and reading multi-level data, particularly in non-volatile memory systems, where the number of available states is limited by the number of memory cells, leading to suboptimal area efficiency and data storage density.
Innovation Solution
A memory system comprising a plurality of memory cells connected in series and parallel configurations, with a memory controller that programs and reads data by manipulating voltage differences across the cells, allowing each group of cells to represent multiple states through effective resistance measurements, thereby exceeding the number of available states beyond the number of individual cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional non-volatile memory cells are used to store multi-level data, then data retention is improved, but the number of available states is limited by the number of memory cells, reducing area efficiency
Solution Approach 1:
The patent combines multiple memory cells into a single memory unit where the collective resistance of the unit represents multi-level data. By merging N memory cells into one functional unit and using the total resistance to represent multiple states, the system achieves more available states than individual cells while maintaining non-volatile data retention properties.
Solution Approach 2:
The memory unit serves multiple functions: it stores data non-volatily like traditional memory cells, but also represents multiple data states through collective resistance measurement. This multi-functionality allows the same hardware structure to achieve both reliable data retention and increased state capacity without requiring separate systems.
2Quantity of substance
If more memory cells are added to increase data storage capacity, then storage density is improved, but the hardware footprint increases, reducing area efficiency
Solution Approach 1:
Multiple memory cells are merged into functional units where N cells represent a single multi-level state. This merging allows the system to store more data (increasing quantity of information) while using fewer physical cell structures, thereby reducing the overall hardware footprint and improving area efficiency.
Solution Approach 2:
The patent transitions from storing one bit per cell to storing multiple bits per cell group by measuring collective resistance. This dimensional change in data representation allows N cells to represent 2^N states, exponentially increasing storage capacity without linearly increasing hardware footprint.
3Ease of operation
If individual memory cells are used to represent each data state, then reading simplicity is maintained, but the number of representable states is limited, reducing productivity
Solution Approach 1:
The patent maintains reading simplicity by measuring the collective resistance of a memory unit as a single value, which directly corresponds to the stored multi-level data. This single measurement approach preserves operational ease while enabling the unit to represent multiple states, thereby improving data retrieval efficiency without complicating the read process.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables area-efficient storage and reading of multi-level data by increasing the number of representable states, allowing for more data to be stored in a smaller hardware footprint, and facilitates prompt data retrieval through a single current measurement.
Implementation Method 1
A memory controller may be configured to apply a voltage difference across a group of memory cells to read multi-level data stored by the group of memory cells based on an effective resistance of the group of memory cells
Data Source
AI summary
Disclosed herein are related to a memory system and a method of operating the memory system. In one aspect, resistances of a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell are individually set. In one aspect, the first memory cell and the second memory cell are coupled to each other in series between a first line and a second line, and the third memory cell and the fourth memory cell are coupled to each other in series between the second line and a third line. In one aspect, current through the second line according to a parallel resistance of i) a first series resistance of the first memory cell and the second memory cell, and ii) a second series resistance of the third memory cell and the fourth memory cell is sensed. According to the sensed current, multi-level data can be read.