Memory Cell Grouping for High Density

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Solution Overview

Problem

Existing memory devices face challenges in scaling down select device dimensions without compromising memory density, as each select device is typically coupled to only one memory cell, limiting spatial efficiency and memory depth.

Innovation Solution

The memory device organizes memory cells into groups, where first electrodes are individually addressable via address lines and second electrodes are commonly addressable via a shared select device within each group, allowing for unique addressing of each memory cell without scaling down select device dimensions, thereby increasing memory depth and density.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If each select device is coupled to only one memory cell, then individual addressing is simplified, but memory density and depth are limited due to spatial constraints

Engineering Contradiction:
Improvememory densityVSAvoidaddressing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the memory cell array into multiple memory cell groups, where each group shares a common select device. This segmentation allows multiple memory cells to be addressed through a single select device by combining group selection with individual cell addressing within the group, thereby increasing memory density without requiring a proportional increase in select devices.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces a hierarchical addressing structure that adds a group dimension to the traditional cell-level addressing. By organizing memory cells into groups that share select devices, the system transitions from a flat one-to-one mapping to a two-level hierarchy, enabling more efficient spatial utilization and increased memory depth.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Quantity of substance

If select device dimensions are scaled down to increase memory density, then more memory cells can be packed, but select device performance and reliability deteriorate

Engineering Contradiction:
Improvememory densityVSAvoidselect device reliability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The patent merges multiple memory cell selections into a single select device by implementing shared select devices across memory cell groups. This merging allows select devices to maintain larger, more reliable dimensions while still achieving high memory density through the group-based organizational structure.

Inventive Principle:
Principle #5Merging (Combining)

3Quantity of substance

If memory cells are organized into groups with shared select devices, then memory depth and density increase, but addressing complexity increases

Engineering Contradiction:
Improvememory densityVSAvoidaddressing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments the addressing process into two distinct levels: group-level selection and individual cell selection within the group. This segmentation of the addressing function allows the system to manage complexity by breaking down the multi-cell selection process into manageable stages, making the enhanced memory density achievable without overwhelming addressing complexity.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS7830709B2Integrated circuit, method of reading data stored within a memory device of an integrated circuit, method of writing data into a memory device of an integrated circuit, memory module, and computer program
Publication Date: 2010.11.09 SAMSUNG ELECTRONICS CO LTD
  • US7830709B2 patent drawing
  • US7830709B2 patent drawing
  • US7830709B2 patent drawing

AI summary

A memory device comprises a plurality of memory cells, each of which comprising a first electrode, a second electrode and an active material arranged between the first electrode and the second electrode, wherein the memory cells are grouped into memory cell groups, each memory cell group defining a memory cell group area and being configured such that corresponding first electrodes are individually addressable, and corresponding second electrodes are commonly addressable via a common select device provided within the memory cell group area of the memory cell group.