Memory Cell Hybrid SLC TLC QLC Programming Without Erase
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Solution Overview
Problem
Memory devices face limitations in programming efficiency as they reach capacity in single-level cell (SLC) and triple-level cell (TLC) formats, leading to performance degradation when switching to quad-level cell (QLC) mode without efficient data migration strategies.
Innovation Solution
A hybrid programming technique that initially operates in high-performance SLC mode, switches to medium-performance TLC mode without erasing data, and further switches to low-performance QLC mode when TLC limits are reached, allowing for continuous data programming by reconfiguring memory cells through multiple program loops and verify pulses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If memory cells are programmed to SLC format to achieve high programming performance, then programming speed is improved, but storage capacity is limited
Solution Approach 1:
The memory device dynamically switches between different operating modes (SLC, TLC, QLC) based on the programming workload. The system transitions from high-performance SLC mode to medium-performance TLC mode when SLC capacity is exhausted, and further transitions to low-performance QLC mode when TLC capacity is reached, allowing the storage system to adapt its performance characteristics to match changing storage requirements
Solution Approach 2:
The invention changes the fundamental parameter of bits per memory cell from 1 (SLC) to 3 (TLC) to 4 (QLC) to resolve the capacity limitation. This parameter transformation allows the system to maintain operational functionality while increasing storage density, accepting the trade-off of reduced programming speed in exchange for increased capacity
2Quantity of substance
If memory cells are switched from SLC to TLC format to increase capacity, then storage capacity is improved, but programming performance degrades
Solution Approach 1:
The invention segments the programming process into distinct phases corresponding to different storage modes. The system first completes SLC programming operations, then transitions to TLC programming for additional capacity, and finally to QLC programming for maximum capacity. This segmentation allows the system to optimize for capacity in later phases while accepting reduced efficiency, as each phase serves a specific storage requirement
3Speed
If data is rewritten from SLC to TLC format without erase to maintain performance, then programming speed is maintained, but data integrity risks increase
Solution Approach 1:
The system performs preliminary actions by completing full SLC programming operations first, establishing a solid data foundation before transitioning to TLC mode. The controlled transition sequence ensures that data is properly established in the higher-density format without risking integrity, as the preliminary SLC programming creates a stable baseline that guides the subsequent TLC programming process
4Quantity of substance
If memory blocks are erased before QLC programming to enable high-density storage, then storage capacity is improved, but operation time increases
Solution Approach 1:
The invention applies local quality by erasing only specific memory blocks that need to be converted to QLC format, rather than erasing entire memory arrays. This selective erasure approach minimizes the total operation time while still enabling the necessary capacity expansion in the target blocks. The system identifies and processes only the specific regions requiring QLC conversion, reducing unnecessary erase operations
Data Source
AI summary
The memory device has a plurality of memory blocks including a plurality of memory cells arranged in a plurality of word lines. The memory device also includes control circuitry that is in communication with the plurality of memory blocks. The control circuitry is configured to receive a data write instruction. The control circuitry is further configured to program the memory cells of the memory blocks to an SLC format. In response to the data programmed to the memory cells of the memory blocks in the SLC format reaching an SLC limit prior to completion of the data write instruction, without erasing the memory cells programmed to the SLC format, the control circuitry is configured to program the memory cells of at least some of the plurality of memory blocks from the SLC format to a TLC format.