Memory Cell With Independently-Sized Switch And Memory Elements
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Solution Overview
Problem
Current memory device fabrication challenges include reducing device size, increasing storage density, reducing power consumption, and lowering costs, particularly in achieving independent sizing of switch and memory elements in memory cells to optimize electrical properties without undue stress on the switch element.
Innovation Solution
The implementation of a memory cell architecture in a cross-point memory array where the switch element dimensions are independent from the memory element dimensions, allowing for various combinations and improved current density in the memory element without affecting the switch element, using phase change material (PCM) and employing dry etch patterning in two perpendicular directions to control stack dimensions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory element size is reduced to increase storage density, then storage density is improved, but the switch element experiences undue stress and electrical property degradation
Solution Approach 1:
The patent divides the memory cell into two independently sized components: a first memory element and a second memory element. The first memory element maintains a larger size to ensure adequate current flow and protect switch element stress, while the second memory element is reduced in size to increase overall storage density. This segmentation allows each component to be optimized for its specific function without compromising the other.
Solution Approach 2:
Different regions of the memory cell are assigned different sizes based on their functional requirements. The first memory element is sized to provide sufficient current for switch operation, while the second memory element is sized smaller for density optimization. This local differentiation of quality (size) resolves the contradiction between density and reliability.
2Volume of moving object
If the device size is reduced to decrease memory device footprint, then device size is improved, but manufacturing precision and electrical property optimization become more difficult
Solution Approach 1:
The memory cell is segmented into multiple elements that can be independently sized. This allows the overall device footprint to be reduced while maintaining adequate dimensions for critical components. The first memory element can be kept larger for manufacturing tolerance, while other elements are reduced for density.
Solution Approach 2:
The patent changes the size parameter of different memory elements independently. By allowing each element to have different dimensions, the design can optimize for both small overall device size and adequate manufacturing precision for individual elements. Critical elements maintain larger dimensions for manufacturing control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of memory cells with optimized electrical properties by allowing independent sizing of switch and memory elements, enhancing storage density and reducing power consumption while maintaining the operational integrity of the switch element.
Implementation Method 1
using phase change material (PCM)
Implementation Method 2
employing dry etch patterning in two perpendicular directions to control stack dimensions
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
Memory cell architectures are described. An example memory cell includes a chalcogenide switch element (610B), and a chalcogenide memory element (614) formed in series with the switch element. A portion of the sidewalls (615) of the chalcogenide switch element are etched such that the smallest lateral dimension of the chalcogenide switch element is different from the lateral dimension of the chalcogenide memory element. In a preferred implementation, the lateral dimension of the chalcogenide memory element is a smallest lateral dimension of the chalcogenide memory element and wherein the smallest lateral dimension of the chalcogenide switch element is less than the smallest lateral dimension of the chalcogenide memory element.