Memory Cell Structure With Tapered Electrodes to Prevent Insulation Voids

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Conventional memory devices experience void formation during the deposition of interfacial insulation layers due to the high density of memory cells, which degrades performance and reliability.

Innovation Solution

The memory device incorporates memory cells with specific width and height ratios and tapered side surfaces to facilitate the stacking of insulation layers, preventing void formation by ensuring W1>W3>W2 and H2>H1>H3, with taper angles less than 82 degrees.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If memory cells are arranged at high density to increase storage capacity, then productivity and storage capacity improve, but voids form in insulation layers during deposition, degrading reliability

Engineering Contradiction:

Improvestorage capacityVSAvoidinsulation layer quality

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

The memory cell structure is segmented into distinct width zones (W1 at bottom, W2 at top electrode, W3 at contact wire) and height zones (H1 for memory cell, H2 for contact wire, H3 for insulation layer thickness), allowing each segment to be optimized independently to prevent void formation while maintaining high density

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent changes geometric parameters of the memory cell structure, specifically implementing tapered side surfaces with angles between 10-80 degrees and establishing specific width relationships (W1>W3>W2) and height relationships (H2>H1>H3), which transforms the deposition process to eliminate voids while preserving high storage capacity

Inventive Principle:

Principle #35Parameter changes

2Ease of manufacture

If conventional memory cell structures are used to simplify manufacturing, then ease of manufacture improves, but voids form during insulation layer deposition

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidinsulation layer quality

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The memory cell structure is pre-configured with tapered side surfaces and specific width/height ratios before insulation layer deposition, which proactively prevents void formation during the subsequent deposition process, eliminating the need for complex post-processing or specialized deposition techniques

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20260013407A1Memory device having improved memory cell structures to prevent formation of voids therein

Publication Date: 2026.01.08 HEFEI RELIANCE MEMORY LTD

AI summary

A memory device includes a memory cell comprising a bottom electrode, a top electrode, and a dielectric layer interposed between the bottom electrode and the top electrode. The bottom electrode has a first width W1. The top electrode has a top surface that has a second width W2 between two edges of the top surface. The memory cell has a first height H1 extending from a lower surface of the bottom electrode to the top surface of the top electrode. The memory device further includes a top contact wire coupled to the top electrode. The top contact wire has a top surface that has a third width W3, a second height H2 at a location between two adjacent memory cells, and a third height H3 extending between the top surface of the top contact wire and the insulating layer, where W1>W3>W2 and H2>H1>H3.