Memory Cell Isolation Layout Using Single-EUV Patterning
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high integration while maintaining reliability and simplifying the manufacturing process.
Innovation Solution
The semiconductor memory device incorporates a substrate with active regions, word lines, cell pad patterns, bit line structures, and isolation insulating patterns, including isolation insulating line and spacer portions, which are formed using a single EUV lithography process to enhance integration and insulation, thereby simplifying manufacturing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography processes are used for forming isolation insulating patterns, then manufacturing complexity increases, but integration density and reliability are compromised
Solution Approach 1:
The patent combines the formation of isolation insulating patterns with the formation of bit line structures into a single EUV lithography process. The isolation insulating patterns and bit line structures are formed simultaneously in the same lithography step, eliminating the need for separate lithography processes and thereby reducing manufacturing complexity while maintaining high precision
Solution Approach 2:
The EUV lithography process serves multiple functions: it forms both the isolation insulating patterns and the bit line structures in a single step. This multi-functional approach reduces the total number of lithography steps required, simplifying the overall manufacturing process while achieving the required precision for both structures
2Productivity
If isolation insulating patterns are formed separately from bit line structures, then manufacturing steps increase, but pattern precision may be compromised
Solution Approach 1:
The patent merges the formation of isolation insulating patterns and bit line structures into a single EUV lithography step. This simultaneous formation improves productivity by reducing the number of manufacturing steps while maintaining high pattern precision through the advanced resolution capabilities of EUV lithography
3Area of moving object
If integration density is increased, then device size is reduced, but insulation reliability between components deteriorates
Solution Approach 1:
The patent applies local quality by forming isolation insulating patterns with specific structural characteristics (including recessed portions) at critical locations between bit line structures. This localized structural optimization provides enhanced insulation reliability in high-density regions where component spacing is minimized, thereby maintaining reliability while enabling reduced device area
Data Source
AI summary
A semiconductor memory includes a substrate having a plurality of active regions, a plurality of word lines formed in the substrate and disposed in a plurality of word line trenches extending in a first direction, a plurality of cell pad patterns on the plurality of active regions, a plurality of bit line structures formed on the substrate and extending in a second direction perpendicular to the first direction, and a plurality of isolation insulating patterns filling at least a portion of a plurality of isolation trenches extending between the plurality of cell pad patterns in the second direction, wherein each of the plurality of isolation insulating patterns includes an isolation insulating line portion and an isolation insulating spacer portion connected to each other and forming an integral body. The isolation insulating line portion and the isolation insulating spacer portion being disposed in alternating ones of the plurality of isolation trenches and extend in the second direction.