3D Memory Cell Isolation via Segmented Insulating Structures
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Solution Overview
Problem
As the integration degree of memory cells in 3D semiconductor memory devices increases, the distance between memory cells in the stacking direction decreases, leading to deteriorated operational reliability.
Innovation Solution
The semiconductor memory device includes a channel layer, a tunnel insulating layer, interlayer insulating structures, conductive layers, data storage patterns, a liner insulation pattern, and a blocking insulating layer. The data storage patterns are spaced apart and correspond to the conductive layers, with the liner insulation pattern covering the surfaces of the data storage patterns and the blocking insulating layer interposed between the conductive layers and the liner insulation pattern.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration degree of memory cells is increased to achieve higher capacity, then the storage capacity is improved, but the distance between memory cells decreases leading to deteriorated operational reliability
Solution Approach 1:
The patent segments the continuous insulating layer into multiple distinct insulating structures (first insulating structures and second insulating structures) that are alternately arranged with conductive layers. This segmentation creates spatial separation between adjacent memory cells, reducing interference while maintaining high integration density. The insulating structures are divided into different types (first and second) with different positions and functions, allowing optimized spacing and electrical isolation.
Solution Approach 2:
The patent introduces insulating structures as intermediary elements between adjacent memory cells and conductive layers. These insulating structures act as mediators that provide electrical isolation and prevent interference between neighboring cells. Specifically, the first insulating structures are positioned between adjacent memory cells, and the second insulating structures are positioned between the conductive layer and the tunnel insulating layer, creating multiple levels of isolation.
2Reliability
If multiple insulating structures and conductive layers are alternately arranged to reduce interference, then the operational reliability is improved, but the device structure becomes more complex
Solution Approach 1:
The patent merges multiple functions into the alternately arranged insulating and conductive layer structure. The first insulating structures serve both as electrical isolation between memory cells and as part of the overall insulating matrix. The second insulating structures simultaneously provide isolation between the conductive layer and tunnel insulating layer while maintaining structural integrity. This merging reduces the need for additional separate isolation structures, managing complexity while achieving reliability.
Solution Approach 2:
The patent extends the isolation architecture into multiple dimensions by arranging insulating and conductive layers alternately in the stacking direction (vertical dimension). This creates a three-dimensional alternating pattern where insulating structures are positioned both horizontally (between adjacent cells) and vertically (between different layers). This multi-dimensional arrangement provides comprehensive isolation without requiring excessive lateral space, managing structural complexity through spatial efficiency.
Data Source
AI summary
Provided herein is a semiconductor memory device and a method of manufacturing the same. The semiconductor memory device includes a plurality of interlayer insulating structures, a plurality of conductive layers alternately stacked with the plurality of interlayer insulating structures, a plurality of data storage patterns spaced apart from each other in a direction in which the plurality of interlayer insulating structures and the plurality of conductive layers are alternately stacked, and a blocking insulating layer or blocking insulation pattern interposed between each data storage pattern and a corresponding conductive layer.