Multi-Level Memory Cell Encoding to Cut Read and Program Latency
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Solution Overview
Problem
As the number of levels per memory cell in non-volatile memory increases, program and read operations experience increased latencies due to the need for finer control of program and verify pulses and a linear increase in reference comparisons, leading to higher power consumption and operation time.
Innovation Solution
A method that involves converting a P-length string into a Q-length string by eliminating at least one level from the L levels in multi-level memory cells, allowing the Q-length string to be programmed using fewer levels, thereby reducing latency and power consumption, and utilizing a level reduction encoder and decoder for this conversion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of levels per memory cell is increased to improve storage capacity, then the storage density is improved, but the program and read operation latencies increase
Solution Approach 1:
The patent segments the data storage across multiple memory cells rather than using all levels in a single cell. By dividing the Q-length string across multiple cells and using only I levels per cell (where I < L), the system achieves efficient storage without the latency penalty of full MLC operation. This segmentation allows parallel operations and reduces the critical path for program and verify pulses.
Solution Approach 2:
The patent changes the operational parameters by using a subset of available levels (I levels out of L total levels) in each memory cell. This parameter adjustment transforms the operation from a full L-level MLC operation to a reduced I-level operation, directly reducing the number of reference comparisons and pulse adjustments needed, thereby reducing latency while maintaining effective storage capacity through the Q-length string distribution.
2Quantity of substance
If the number of levels per memory cell is increased to improve storage capacity, then the storage density is improved, but the power consumption increases
Solution Approach 1:
The patent segments the storage operation across multiple memory cells, each operating at reduced levels. This segmentation reduces the power required per cell since fewer program and verify pulses are needed when using I levels instead of L levels. The distributed architecture allows power-efficient operation while maintaining overall storage capacity through the Q-length string.
Solution Approach 2:
The patent changes the operational parameter from L levels to I levels per memory cell, where I < L. This parameter reduction directly decreases the power consumption for program and verify operations in each cell, as the fine control requirements and number of reference comparisons are reduced. The system compensates for the reduced per-cell capacity by distributing data across more cells in the Q-length string.
3Measurement precision
If the number of reference comparisons is increased to improve read accuracy in MLC, then the reading precision is improved, but the operation time increases
Solution Approach 1:
The patent changes the parameter from L reference comparisons (required for full L-level MLC) to I reference comparisons (where I < L). This parameter reduction directly decreases the operation time for read activities while maintaining sufficient read accuracy through the distributed Q-length string architecture. The system achieves this by operating each cell at reduced levels with corresponding fewer reference voltages needed.
4Manufacturing precision
If fine control of program and verify pulses is applied to improve programming accuracy, then the manufacturing precision is improved, but the operation time and power consumption increase
Solution Approach 1:
The patent changes the operational parameter from requiring fine control for L levels to requiring fine control for only I levels (where I < L). This parameter reduction decreases the number of discrete pulse adjustments needed, thereby reducing operation time and power consumption while maintaining adequate programming accuracy for the reduced level operation. The distributed Q-length string compensates for the reduced per-cell precision requirements.
Data Source
AI summary
A method of operating a memory device is provided. The memory device includes a plurality of multi-level memory cells of which each memory cell includes L levels. Data which is expressed in a binary number is received. A P-length string is generated from the data. The P-length string is converted to a Q-length string. The Q-length string is distributed using I levels by eliminating at least one level from the L levels. P and Q represent binary bit lengths of the P-length string and the Q-length string. Q is greater than P. L represents a maximum number of levels which each multi-level memory cell has. I is smaller than L. The Q-length string is programmed into the plurality of memory cells.