Memory Cell Layout with Segmented Pad Columns for Signal Delay Reduction
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Solution Overview
Problem
The challenge in semiconductor memory devices is to increase the number of pads without enlarging the chip size, while maintaining the area for signal lines and reducing signal delay.
Innovation Solution
The solution involves arranging pads in separate columns outside the memory cell array, with signal lines formed perpendicular to the subarray columns, directly connecting pads to input circuits, thereby minimizing chip size and reducing signal delay.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If pads are arranged in the middle section of the subarray matrix to increase the number of pads, then the number of pads increases, but the area for signal lines is reduced and signal delay increases
Solution Approach 1:
The pad arrangement is segmented into two distinct columns: a first pad column outside the memory cell array and a second pad column inside the memory cell array. This segmentation allows signal lines to be routed through different spatial zones, separating pad functions from signal line routing areas, thereby increasing pad capacity without compromising signal line area or increasing signal delay.
2Quantity of substance
If pads are arranged in the middle section of the subarray matrix, then the number of pads increases, but the area for signal lines is reduced
Solution Approach 1:
The invention utilizes the spatial dimension by arranging pads in columns that extend in the row direction, creating a vertical arrangement that separates pad occupation from horizontal signal line routing. The first pad column is positioned outside the memory cell array while the second pad column is positioned inside, effectively using the depth dimension to accommodate more pads without encroaching on the horizontal signal line area.
3Ease of operation
If signal lines are routed through pad areas to connect peripheral circuits to subarrays, then circuit connectivity is achieved, but signal delay increases due to longer path length
Solution Approach 1:
The invention extracts the signal line routing function from the pad area by creating dedicated signal line regions that bypass the pad columns. Signal lines are routed directly from peripheral circuits to subarrays through areas not occupied by pads, separating the connectivity function from the pad occupation zones and thereby reducing signal path length and delay.
Data Source
AI summary
A semiconductor memory device includes a memory cell array divided into a plurality of subarrays arranged in matrix form, the plurality of subarrays making up a plurality of subarray columns, an address pad column formed outside the memory cell array, the address pad column comprising a plurality of address pads that are arranged to be substantially parallel to the subarray columns, a data I/O pad column formed in a middle section of the memory cell array, the data I/O pad column comprising data I/O pads that are arranged to be substantially parallel to the subarray columns, an address input circuit arranged in the middle section of the memory cell array, and a pad input address line formed in a direction substantially perpendicular to the subarray columns on the memory cell array, the pad input address line directly connecting the address pad and the address input circuit.