Memory Cell Leakage Reduction via Dummy Gate Enclosure

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Solution Overview

Problem

The performance of existing multiple time programmable (MTP) non-volatile memory cells is not stable due to leakage current generated by the breakdown between the source region and the well region, which deteriorates the reliability of the memory cells.

Innovation Solution

A fabrication method that includes forming a select gate structure, a floating gate structure, and a dummy gate structure on a substrate with lightly doped regions, where the dummy gate structure ensures the source region is entirely enclosed by the lightly doped region, preventing direct contact with the well region and thus reducing leakage current.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the source region directly contacts the well region in existing MTP NVM structures, then the manufacturing process is simpler, but leakage current occurs due to breakdown between source and well regions, deteriorating reliability

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidmemory cell structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent introduces a dummy gate structure that segments the well region into isolated sections. The dummy gate divides the well region such that the source region is enclosed by lightly doped regions and does not directly contact the well region, preventing breakdown and leakage current while maintaining structural organization

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The dummy gate structure acts as an intermediary element between the source region and the well region. By positioning the dummy gate between these regions and using lightly doped regions as intermediaries, the patent prevents direct contact that would cause breakdown, thereby improving reliability without requiring complete structural redesign

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the source region is enclosed by lightly doped regions with dummy gate structure, then leakage current is prevented and reliability improves, but the device structure becomes more complex

Engineering Contradiction:
Improvememory cell reliabilityVSAvoidgate structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The dummy gate structure serves multiple functions simultaneously: it acts as a structural divider to isolate the well region, provides a platform for forming lightly doped regions that enclose the source region, and prevents breakdown between source and well regions. This multi-functionality allows the additional structure to deliver multiple benefits rather than just adding complexity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The dummy gate structure is formed in advance during the fabrication process, before the source and drain regions are fully defined. This preliminary action establishes the structural framework that guides subsequent doping steps, ensuring that lightly doped regions are correctly positioned to enclose the source region and prevent leakage current

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10062767B2Memory cell and fabrication method thereof
Publication Date: 2018.08.28 SEMICON MFG INT (SHANGHAI) CORP
  • US10062767B2 patent drawing
  • US10062767B2 patent drawing
  • US10062767B2 patent drawing

AI summary

Memory cells and fabrication methods thereof are provided. An exemplary method includes providing a substrate having a well region; forming a select gate structure, a floating gate structure and a dummy gate structure on a surface of the well region; forming a first lightly doped region, a second lightly doped region and a third lightly doped region in the well region, the first lightly doped region and the second lightly doped region being at two sides of the select gate structure respectively, the second lightly doped region being in between the select gate structure and the floating gate structure, and the third lightly doped region being in between the floating gate structure and the dummy gate structure; and forming bit line region in the first lightly doped region and a source region in the third lightly doped region, the source region being enclosed by the third lightly doped region.