Memory Cell Leakage Isolation via Segmented Transistor Design
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Solution Overview
Problem
Multiple-time programmable (MTP) non-volatile memory (NVM) devices face challenges in preventing leakage current, which affects the proper functioning of selected memory cells during write, read, and erase operations due to unselected memory cells generating leakage currents.
Innovation Solution
The novel memory cell design includes a capacitor and two transistors, where the second transistor is turned off when the memory cell is not selected, preventing leakage current by ensuring no current passes through even if a voltage drop exists between terminals VD and VS, thus isolating the selected memory cell from unselected cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If MTP NVM devices use a conventional memory cell design, then the device structure is simpler and manufacturing is easier, but leakage current from unselected memory cells affects the proper functioning of selected memory cells
Solution Approach 1:
The memory cell is segmented into multiple functional components: a capacitor for charge storage, a first transistor for read/write control, and a second transistor specifically for leakage current control. This segmentation allows each component to perform its dedicated function, with the second transistor acting as an isolation switch that prevents leakage current from unselected cells from affecting selected cells during operations.
2Object-generated harmful factors
If the memory cell includes additional transistors and capacitors to control leakage current, then leakage current is reduced, but the memory cell size increases
Solution Approach 1:
The patent merges the leakage control function with the existing memory cell structure by integrating the second transistor into the cell's transistor network. The second transistor shares the same physical space and interconnect structure as other cell components, allowing leakage control without proportionally increasing the cell area. Multiple cells also share common bit lines and word lines, further reducing the per-cell area overhead.
Data Source
AI summary
A memory system is provided. The memory system includes a number of memory cells and a number of bit lines. The memory cells are interlocked with each other in rows and columns. The memory cells include respective capacitors, respective first transistors and respective second transistors. Respective upper plates of the respective capacitors are electrically connected to respective gates of the respective first transistors, and respective drains of the respective second transistors are connected to respective sources of the respective first transistors. The bit lines are arranged along an extending direction of the rows. Respective bit lines are connected to the respective first transistors through respective bit-line contacts, and each of the respective bit-line contacts is shared by two adjacent memory cells of the extending direction of the rows.