Isolation-Structured Memory Cell Layout for Leakage Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in reducing threshold voltage decrease and leakage current issues due to impurity absorption in the insulating layer during manufacturing, particularly in high withstand voltage transistors, which limits the decrease in element-to-element pitch and increases transistor area-to-chip area ratio.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a first insulating layer adjacent to the transistor, a second insulating layer between the first insulating layer and a conductive layer, and a semiconductor layer with a hammerhead type planar shape, which reduces leakage current by increasing channel length and preventing impurity absorption, thereby maintaining threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the element-to-element pitch is reduced to increase chip efficiency, then more transistors can be packed on the chip, but leakage current increases due to impurity absorption in the insulating layer
Solution Approach 1:
By segmenting the insulating layer into multiple layers with different properties, the structure prevents impurity absorption even when elements are closely spaced. This enables reduced element-to-element pitch while maintaining low leakage current, thus improving chip efficiency without sacrificing reliability.
2Area of stationary object
If the transistor area is reduced to decrease the area-to-chip area ratio, then more transistors fit on the chip, but the insulating layer becomes more susceptible to impurity absorption
Solution Approach 1:
The segmented insulating layer structure provides enhanced protection against impurity absorption even in smaller transistors. Each layer acts as a barrier, ensuring that reduced transistor area does not compromise impurity resistance, allowing higher density packing while maintaining reliability.
Solution Approach 2:
Different insulating layers are positioned at specific locations with different functional requirements. The first insulating layer provides local protection to the channel, while upper layers provide additional barriers, enabling small transistor areas with maintained impurity absorption resistance.
Data Source
AI summary
A semiconductor device includes: a semiconductor substrate; a transistor formed on the semiconductor substrate; a first insulating layer adjacent to the transistor in a first direction along a main surface of the semiconductor substrate, the first insulating layer being formed toward an inside of the semiconductor substrate; a first conductive layer connected to a gate of the transistor, a part of the first conductive layer being opposed to the first insulating layer; a second insulating layer disposed between the first insulating layer and the first conductive layer; and a first semiconductor layer disposed between the second insulating layer and the first conductive layer.