Memory Cell Level Assignment for NAND Flash Error Reduction
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Solution Overview
Problem
Aggressive scaling and increasing bits per cell in multi-level NAND flash memory devices lead to higher error rates, necessitating low-complexity, high-efficiency error reduction methods.
Innovation Solution
A memory system with a memory controller that determines cell level assignments based on error rates, selectively adjusting the assignments to minimize errors by predicting error rates and using permutations of cell levels with lower error rates for writing and reading data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple bits are stored in each memory cell (MLC), then manufacturing costs and performance improve, but error rates increase
Solution Approach 1:
The patent applies preliminary action by determining cell level assignments and predicting error rates before data is written to the memory device. The memory controller analyzes the data to be written, determines optimal level assignments in advance, and prepares error correction strategies beforehand, rather than reacting to errors after they occur.
Solution Approach 2:
The patent changes parameters by dynamically adjusting cell level assignments based on the specific data being written. Instead of using fixed level assignments, the system varies the voltage levels and their permutations according to the data pattern, thereby optimizing the distribution of data across different voltage states to minimize error rates.
2Reliability
If error correction codes are used to handle more errors, then reliability improves, but circuit area and power consumption increase
Solution Approach 1:
The patent applies partial action by using selective error correction strategies rather than applying full error correction codes to all data uniformly. The system identifies specific cell levels and data patterns that are prone to errors and applies correction measures only where needed, based on predicted error rates for different level assignments.
Solution Approach 2:
The patent changes the approach from using fixed error correction codes to dynamically adjusting cell level assignments as a form of error mitigation. By varying the voltage level permutations based on data characteristics, the system reduces the burden on error correction circuits, thereby reducing their required complexity and resource consumption.
3Reliability
If cell level assignment is optimized for specific data patterns, then error rate decreases, but processing complexity increases
Solution Approach 1:
The patent applies preliminary action by performing error rate prediction and level assignment optimization before the actual write operation. The memory controller analyzes the data pattern, predicts error rates for different level assignments, and selects the optimal assignment in advance, so that during the actual write operation, the optimized assignment is already in place without adding real-time processing complexity.
Data Source
AI summary
A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory cells. The memory controller is configured to manage the memory device using a cell level assignment with respect to a plurality of memory cell levels, determine a cell count for each of the cell levels associated with original data of the memory device that is to be accessed, predict an error rate from the cell counts, and selectively adjust the cell level assignment based on the error rate.