3D Memory Cell Liner Structure for Impurity Diffusion Control
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing semiconductor devices face limitations in integration density and operational reliability due to the challenges in stacking memory cells and preventing external impurity diffusion during manufacturing.
Innovation Solution
A semiconductor device structure and manufacturing method that include a liner pattern with distinct portions containing halide impurities at different concentrations, which are deposited using specific plasma treatment processes to enhance the density and reduce impurity diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single-layer memory cell structure is used, then the manufacturing process is simple, but the integration density reaches a limit
Solution Approach 1:
The patent transitions from a single-layer memory cell structure to a three-dimensional stacked structure with multiple memory cells arranged in vertical layers. This dimensional change allows multiple memory cells to occupy the same footprint area on the substrate, thereby significantly increasing integration density while maintaining manufacturing feasibility through sequential deposition processes
2Quantity of substance
If memory cells are stacked in three dimensions, then the integration density improves, but the operational reliability deteriorates due to impurity diffusion
Solution Approach 1:
The patent introduces a liner layer as an intermediary barrier between adjacent stacked memory cells. This liner layer, positioned on the sidewalls of the memory cells, prevents external impurities from diffusing into the memory cell structures during manufacturing and operation, thereby maintaining operational reliability in the three-dimensional stacked configuration
Solution Approach 2:
The patent applies different material compositions to different regions of the liner layer. The first portion of the liner layer contains halide impurities at a first concentration, while the second portion contains halide impurities at a second concentration lower than the first concentration. This local quality variation optimizes both the barrier properties and the overall device performance
3Ease of manufacture
If a uniform liner layer is used, then the manufacturing process is simple, but the impurity diffusion protection is insufficient
Solution Approach 1:
The patent creates a liner layer with non-uniform halide impurity distribution, where the first portion has a higher halide impurity concentration and the second portion has a lower halide impurity concentration. This local quality variation enhances the barrier effect against impurity diffusion while maintaining a relatively simple deposition process using plasma-enhanced chemical vapor deposition
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed solution achieves a stable semiconductor device structure with improved reliability by minimizing impurity diffusion and optimizing the deposition process, thereby enhancing the integration density and operational performance.
Implementation Method 1
a liner pattern located over a sidewall of the memory cell and including a first portion and a second portion, the first portion including halide impurities at a first concentration, the second portion including halide impurities at a second concentration that is lower than the first concentration
Implementation Method 2
forming a liner layer on the buffer layer, the liner layer including a first portion and a second portion, the first portion including halide impurities at a first concentration, the second portion including halide impurities at a second concentration that is lower than the first concentration
Data Source
AI summary
A semiconductor device may include: a first conductive line extending in a first direction; a second conductive line extending in a second direction intersecting the first direction; a memory cell located between the first conductive line and the second conductive line in a third direction that is intersecting to the first and second directions; and a liner pattern located over a sidewall of the memory cell and including a first portion and a second portion, the first portion including halide impurities at a first concentration, the second portion including halide impurities at a second concentration that is lower than the first concentration.