Memory Cell Bistable Circuit for Low-Voltage Data Retention
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Solution Overview
Problem
Existing memory circuits, such as VNR-SRAMs and NV-SRAMs, face limitations in reducing power consumption and energy consumption during power gating (PG) due to leakage current and mode switching overhead, which increases the break-even time (BET).
Innovation Solution
The proposed electronic circuit includes a cell array with memory cells having bistable circuits that can switch between two modes, allowing for reduced power consumption by shutting down unnecessary memory cells and using a lower power supply voltage for retaining data in the second mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by stationary object
If ULV retention is performed on all memory cells during power gating, then standby power is reduced, but leakage current and mode switching energy increase the break-even time
Solution Approach 1:
The cell array is divided into multiple blocks, and each block is independently controlled. The control circuit identifies store-free blocks (containing only dirty data) and applies power gating selectively to these blocks while maintaining other blocks in normal operation, thereby reducing overall standby power without requiring mode switching of all cells
Solution Approach 2:
The invention extracts and identifies store-free blocks from the cell array using dirty bit information. These store-free blocks are separated from the main array and subjected to power gating independently, removing the need for mode switching overhead from the entire array and reducing break-even time
2Reliability
If store operation is performed on all memory cells, then data is retained after power gating, but energy consumption and latency increase for unnecessary data
Solution Approach 1:
The invention uses dirty bit feedback to track which memory cells contain modified data. The control circuit continuously monitors dirty bit states and uses this information to identify store-free blocks, enabling selective power gating decisions that maintain data retention reliability while minimizing energy consumption by avoiding store operations on clean blocks
Data Source
AI summary
An electronic circuit includes a cell array including memory cells each including a bistable circuit that includes first and second inverter circuits, each having a first mode characterized by there being substantially no hysteresis in transfer characteristics and a second mode characterized by there being hysteresis in the transfer characteristics, and being switchable between the first and second modes, and a control circuit configured to, after powering off a first memory cell that store data that are not required to be retained, put the bistable circuit in a remaining second memory cell into the second mode, and supply a second power supply voltage that allows the bistable circuit in the second mode to retain data and is lower than a first power supply voltage supplied to the bistable circuit when data is read and/or written, to the bistable circuit in the second memory cell while maintaining the second mode.