Nonvolatile Memory Cell Structure for Mask Reduction
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Solution Overview
Problem
Conventional nonvolatile semiconductor memory devices face challenges in miniaturization and process complexity due to the need for multiple masks in forming resistance variable elements, leading to increased costs and reduced integration density.
Innovation Solution
A nonvolatile semiconductor memory device with a simplified 1T1R-type memory cell structure, where the upper electrode and wire, as well as the lower electrode and contact plug, are constituted by identical constituents, allowing the resistance variable layer to be formed with only one additional mask in a standard Si semiconductor process, thereby reducing the number of process steps and enhancing miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If conventional methods are used to form resistance variable elements with separate upper electrodes and wires, then the structure is more robust, but the number of masks increases and miniaturization is hindered
Solution Approach 1:
The patent merges the upper electrode and wire into a single conductive structure, and the lower electrode and contact plug into another single structure. This consolidation reduces the number of separate components that would require separate masking steps, thereby reducing the total number of masks needed while enabling further miniaturization of the memory cell
2Ease of manufacture
If conventional resistance variable elements are formed with multiple separate components, then electrical connection is more reliable, but manufacturing cost increases
Solution Approach 1:
By combining the upper electrode and wire into one structure and the lower electrode and contact plug into another, the patent reduces the number of interfaces and joining steps required. This simplification reduces manufacturing complexity and cost while maintaining electrical connection reliability through the integrated design
3Quantity of substance
If conventional 1T1R memory cells are formed with separate electrode and wire structures, then the design is more flexible, but integration density is reduced
Solution Approach 1:
The integration of upper electrode with wire and lower electrode with contact plug reduces the spatial footprint of each memory cell component. This consolidation allows for higher integration density by reducing the area required per cell while the standardized integrated structure maintains design flexibility for scaling and array configuration
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a reversible and stable rewrite characteristic, high-speed operability, and reduced manufacturing costs, while maintaining compatibility with standard Si semiconductor processes, achieving further miniaturization and integration density.
Implementation Method 1
a nonvolatile semiconductor memory element (resistance variable memory) including as a memory section a resistance variable element which changes resistance values to be retained stably, in response to voltage pulses applied
Data Source
Figure 1(a)~1(b)
Figure 1(c)~1(d)
Figure 1(e)~1(f)
AI summary
A nonvolatile semiconductor memory device (100) comprises a substrate (102) provided with a transistor (101); a first interlayer insulating layer (103) formed over the substrate to cover the transistor; a first contact plug (104) formed in the first interlayer insulating layer and electrically connected to either of a drain electrode (101a) or a source electrode (101b) of the transistor, and a second contact plug (105) formed in the first interlayer insulating layer and electrically connected to the other of the drain electrode or the source electrode of the transistor; a resistance variable layer (106) formed to cover a portion of the first contact plug; a first wire (107) formed on the resistance variable layer; and a second wire (108) formed to cover a portion of the second contact plug; an end surface of the resistance variable layer being coplanar with an end surface of the first wire.