Memory Cell Multi-Stage Erase for Data Retention Stability

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Solution Overview

Problem

Existing memory sub-systems face issues with data retention and read window budget reduction due to charge loss and electron trapping during idle time between programming and erasing phases, leading to cell damage and poor retention properties.

Innovation Solution

Implementing a multi-stage erase operation with a first 'weak' erase sub-operation followed by a 'strong' erase sub-operation to establish an intermediate threshold voltage level during idle time, reducing cell damage and electron trapping.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If a single strong erase operation is performed immediately after programming, then erase speed is improved, but charge loss and electron trapping occur during idle time leading to cell damage and poor retention properties

Engineering Contradiction:

Improveerase speedVSAvoiddata retention

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The erase operation is divided into multiple stages: a first strong erase operation followed by a second weaker erase operation. This segmentation allows the memory cells to be erased in steps, reducing the idle time between programming and complete erasing while maintaining data retention properties by avoiding excessive charge loss and electron trapping that would occur with a single strong erase operation.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first strong erase operation is performed as a preliminary action before the second erase operation. This preliminary erasing action reduces the threshold voltage of the memory cells partially, preparing them for the final erasure while minimizing the idle time period where charge loss and electron trapping would otherwise occur, thus improving data retention.

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If idle time between programming and erasing is extended, then programming completeness is improved, but charge loss and electron trapping increase causing cell damage

Engineering Contradiction:

Improveprogramming completenessVSAvoidcharge loss and electron trapping

Core Design Contradiction:

Manufacturing precisionVSObject-affected harmful factors

Solution Approach 1:

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The erase voltage parameter is changed between the two erase operations. The first erase operation uses a stronger voltage to quickly reduce the threshold voltage, while the second operation uses a weaker voltage to complete the erasure. This parameter change optimizes the balance between programming completeness and minimizing charge loss during the necessary idle time.

Inventive Principle:

Principle #35Parameter changes

Data Source

PatentUS12487752B2Multi-stage erase operation of memory cells in a memory sub-system

Publication Date: 2025.12.02 MICRON TECHNOLOGY INC

AI summary

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.