Nonvolatile Memory Cell Neuron Model Weight Storage
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Solution Overview
Problem
Existing semiconductor storage devices using neuron models face challenges in miniaturization due to difficulties in storing and updating coupling weights, with previous designs consuming high power and having complex structures that are not suitable for miniaturized devices.
Innovation Solution
A semiconductor storage device utilizing nonvolatile semiconductor memory cells with a conductive path, charge storage layer, and control gate electrode to optimize and store the coupling weight of the engineering neuron model, allowing for efficient power management and miniaturization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If neuron MOS or resistor-inverter circuits are used to implement neuron models, then the device can perform weighted coupling operations, but the device cannot store or hold the coupling weight
Solution Approach 1:
The patent combines the neuron model circuit with nonvolatile semiconductor memory cells into a unified structure. The memory cell's floating gate serves dual purposes: storing data and representing the coupling weight in the neuron model. This merging eliminates the need for separate weight storage mechanisms while enabling persistent weight storage.
Solution Approach 2:
The floating gate in the memory cell is designed to serve multiple functions: it acts as both the storage element for memory data and the weight representation element for the neuron model. By making this single component multi-functional, the patent resolves the contradiction between performing weighted coupling operations and storing the weights persistently.
2Adaptability or versatility
If neuron MOS structure with multiple floating gates is used, then weighted coupling can be implemented, but direct control of charge state becomes difficult
Solution Approach 1:
The patent extracts the weight control mechanism from the complex multi-floating-gate neuron MOS structure and implements it through the control gate of a single memory cell. This simplifies the control interface while maintaining the weighted coupling functionality, as the control gate can directly modulate the charge state to represent weight values.
3Adaptability or versatility
If resistor-inverter circuits with large resistance change are used, then neuron model operation is achieved, but power consumption increases
Solution Approach 1:
The patent replaces the resistor-inverter circuit mechanism with a memory cell-based implementation. Instead of relying on large resistance changes in analog circuits, the system uses the digital memory cell's charge storage capability to represent weights, thereby reducing power consumption while maintaining neuron model functionality.
4Reliability
If sophisticated encryption algorithms like RSA are mounted on miniaturized devices, then encryption reliability is improved, but device size and power consumption increase
Solution Approach 1:
The patent changes the fundamental parameter of encryption from complex algorithmic processing to physical/neural computation using the neuron model. By implementing encryption through weighted coupling operations in a neural network rather than traditional cryptographic algorithms, the system achieves security functionality with reduced device size and lower power consumption.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables the miniaturization of security devices by effectively storing and updating coupling weights, reducing power consumption, and enhancing data security through robust nonlinear processing characteristics.
Implementation Method 1
a storage part including a plurality of nonvolatile semiconductor memory cells each having a conductive path, a charge storage layer and a control gate electrode
Data Source
AI summary
A semiconductor storage device includes a storage part including a plurality of nonvolatile semiconductor memory cells each having a conductive path, a charge storage layer and a control gate electrode. The device further includes a plurality of first input terminals each connected to one end of the conductive path of each nonvolatile semiconductor memory cell, a plurality of second input terminals each connected to the control gate of each nonvolatile semiconductor memory cell, and an output end connected to the other ends of the conductive paths of the plurality of nonvolatile semiconductor memory cells, respectively.