Memory Cell Pair Refresh Timing via Statistical Counter
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Solution Overview
Problem
Current memory devices, such as DRAM, require frequent and energy-intensive refreshing of memory cells upon every read operation, leading to increased energy consumption and reduced bandwidth due to their volatile nature.
Innovation Solution
The implementation of memory cell pairs in a non-volatile memory device that stores single bits, allowing for periodic refreshing rather than on every access, using a controller to determine when to perform refresh operations based on statistical selection algorithms, and employing differential cell structures to reduce the need for precise demarcation read voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If frequent refreshing of memory cells is performed to maintain data integrity, then reliability is improved, but energy consumption increases
Solution Approach 1:
The patent implements periodic refreshing of memory cells based on access patterns rather than refreshing on every access. The controller monitors read operations and performs refresh operations at intervals determined by statistical selection algorithms, thereby maintaining data integrity while significantly reducing energy consumption compared to continuous refreshing schemes.
2Reliability
If refreshing is performed on every read operation, then data integrity is maintained, but bandwidth is reduced
Solution Approach 1:
The system performs refresh operations periodically based on monitored access patterns rather than on every read operation. The controller uses statistical selection algorithms to determine when refreshing is necessary, allowing continuous data access for frequently read data while maintaining integrity for less accessed data through periodic refreshes, thereby preserving bandwidth.
3Measurement precision
If precise demarcation read voltages are used to distinguish memory states, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent divides the memory cell into a pair of cells (first and second memory cells) that store complementary data. This segmentation allows the system to determine stored data by comparing the states of the two cells rather than relying on precise voltage thresholds, thereby reducing the complexity of voltage control while maintaining accurate state detection.
Solution Approach 2:
The system uses feedback from comparing the states of paired memory cells to determine the stored data value. By monitoring the relative states of complementary cells and using this feedback for determination, the system achieves accurate measurement without requiring precisely controlled demarcation read voltages, thus reducing device complexity.
Data Source
AI summary
Systems, methods, and apparatus related to memory devices (e.g., storage class memory). In one approach, a memory device has a memory array including memory cells arranged as differential memory cell pairs, with each pair storing a single logical bit. The memory device has a controller that receives a command from a host to initiate a read operation. The memory cell pair is selected using bitlines and a common wordline. A partition of the memory array is accessed to read the data stored by the memory cell pair, and then store the read data in a latch for sending to the host. In response to accessing the partition, a counter is incremented. The controller statistically determines whether to perform a refresh operation for the partition based on comparing the current value of the counter to a value previously generated by a random number generator.