Memory Cell Parallel Current Comparison for Multilevel Data
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Solution Overview
Problem
Semiconductor devices face challenges in writing and reading multilevel data due to variations in transistor characteristics, leading to increased writing time and potential inaccuracies, especially when storing data in a narrow threshold voltage range.
Innovation Solution
A semiconductor device configuration including multiple transistors and capacitors connected through specific wiring arrangements, which allows for the determination of current equality between transistors to stabilize threshold voltage, enabling efficient writing and reading of multilevel data without the need for sequential verification operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multilevel data is stored in a memory cell with narrow threshold voltage range, then storage capacity is improved, but writing time increases extremely long due to sequential verify operations
Solution Approach 1:
The patent replaces the conventional sequential verify operation mechanism with a parallel comparison mechanism using multiple transistors and capacitors. Instead of sequentially reading and comparing data bits, the invention simultaneously compares multiple data values against reference voltages using transistor current ratios, enabling parallel multilevel data writing and significantly reducing writing time while maintaining high storage capacity
Solution Approach 2:
The patent introduces dynamic voltage adjustment during the writing process, where reference voltages are dynamically set based on desired threshold voltage ranges. The writing operation dynamically adjusts gate voltages and channel widths of transistors to achieve precise threshold voltage control for multilevel data, enabling flexible and adaptive writing operations that accommodate narrow voltage ranges
2Device complexity
If conventional memory cell structure is used, then device complexity is low, but manufacturing precision deteriorates due to transistor characteristic variations affecting threshold voltage
Solution Approach 1:
The patent implements a feedback mechanism where the threshold voltage of the memory transistor is continuously monitored and adjusted during the writing operation. The current ratios through multiple transistors provide feedback information about the actual threshold voltage, which is then used to adjust writing parameters to achieve the desired threshold voltage range, compensating for transistor variations
Solution Approach 2:
The patent changes multiple parameters simultaneously to achieve precise threshold voltage control: gate voltages are adjusted to different levels, channel widths of transistors are varied to change current ratios, and reference voltages are modified based on the desired data level. These parameter changes work together to overcome transistor characteristic variations and achieve high manufacturing precision
Data Source
AI summary
To provide a memory cell for storing multilevel data that is less likely to be affected by variations in characteristics of transistors and that is capable of easily writing multilevel data in a short time and accurately reading it out. In writing, a current corresponding to multilevel data is supplied to the transistor in the memory cell and stored as the gate-drain voltage of the transistor in the memory cell. In reading, a current is supplied to the transistor in the transistor with the stored gate-drain voltage, and the multilevel data is obtained from the voltage supplied to generate a current that is equal to the current.