Self-Aligned Memory Cell Pillars With Fewer Lithography Steps
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Solution Overview
Problem
Current semiconductor devices with memory elements face challenges in achieving high integration density, low power consumption, and cost-effectiveness, particularly in the manufacturing process.
Innovation Solution
A method for manufacturing a semiconductor device with a memory element involves forming specific band-shaped material layers and etching them to create a semiconductor pillar, followed by the formation of impurity regions and gate insulating and conductor layers in a self-aligned manner, reducing the number of lithography processes and enhancing integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional memory cell structures are used, then manufacturing process is simpler, but integration density is lower
Solution Approach 1:
The manufacturing process is segmented into distinct stages: forming band-shaped material layers, etching to create semiconductor pillars, forming impurity regions, and forming gate insulating and conductor layers. This segmentation allows each step to be optimized independently while achieving high integration density through the self-aligned nature of the process.
Solution Approach 2:
The invention transitions from planar memory cell structures to three-dimensional vertical structures by forming semiconductor pillars and surrounding gate configurations. This dimensional change enables higher integration density by utilizing vertical space more effectively while maintaining manufacturing feasibility through self-aligned processes.
2Manufacturing precision
If more lithography processes are used, then manufacturing precision is higher, but manufacturing cost increases
Solution Approach 1:
Band-shaped material layers are formed in advance as self-aligned masks before etching the semiconductor pillars. This preliminary action establishes precise alignment for subsequent steps without requiring additional lithography processes, thereby reducing manufacturing cost while maintaining high alignment precision.
Solution Approach 2:
The band-shaped material layers serve as self-aligned masks that automatically define the positions of semiconductor pillars and subsequent structures. This self-service mechanism eliminates the need for separate lithography alignment steps, reducing both manufacturing complexity and cost while achieving high precision.
3Manufacturing precision
If vertical pillar structures are used, then integration density is higher, but manufacturing complexity increases
Solution Approach 1:
Multiple manufacturing steps are merged into a self-aligned sequence where band-shaped material layers are formed, then used as masks for etching pillars, followed by impurity region formation and gate layer deposition. This merging of steps into a unified self-aligned process reduces overall complexity compared to performing each step separately with independent alignment.
Data Source
AI summary
In a semiconductor device including a memory element, a first mask material layer formed in a self-aligned manner and second mask material layers formed on both sides of the first mask material layer are used to form a second gate insulating layer and a second gate conductor layer 35 at the area of the first mask material layer and N layers and N+ layers at the areas of the second mask material layers, and a P-layer semiconductor pillar, a first gate insulating layer, a first gate conductor layer, a second gate insulating layer, a second gate conductor layer, N layers, and N+ layers, which are all elements constituting a memory cell, are formed in a self-aligned manner.