Memory Cell Potential Stabilization Circuit
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in rapidly stabilizing the potential of memory cells, particularly at low temperatures, due to increased leakage current, which prolongs testing times and affects data retention characteristics.
Innovation Solution
A semiconductor device with a memory unit potential controller that includes first and second potential adjustment parts, which supply currents to adjust the potential of the memory cell, allowing for rapid stabilization and reducing testing time without compromising data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the potential of the memory cell is set to a value different from the source potential VSS to reduce leakage current, then the leakage current is reduced, but it takes a considerable time until the potential of the memory cell is stabilized
Solution Approach 1:
The patent applies preliminary action by setting the memory cell potential to an intermediate potential (higher than VSS by about 100 mV) before actual operation or testing. This preliminary potential adjustment reduces leakage current in advance, and the system is designed to accommodate the subsequent stabilization time requirement, thereby preventing excessive leakage during standby while managing the time penalty for potential stabilization.
2Loss of energy
If the memory cell potential is adjusted to reduce leakage current at high temperature, then leakage current is reduced, but the test time is further increased at low temperature and room temperature where leakage current is already smaller
Solution Approach 1:
The patent applies local quality by implementing temperature-dependent potential control. At high temperatures where leakage current is significant, the memory cell potential is set to an intermediate potential (VSS + 100 mV) to reduce leakage. At low temperatures and room temperature where leakage is already minimal, the potential control is adjusted or omitted, thereby applying the leakage reduction technique locally only where it is most needed, avoiding unnecessary time penalties in temperature ranges where it provides minimal benefit.
3Device complexity
If a single potential adjustment method is used for all temperature conditions, then the device structure is simple, but the test time is excessively long at low temperatures
Solution Approach 1:
The patent applies dynamics by making the potential control system adaptive to temperature conditions. The potential control circuit dynamically adjusts the memory cell potential based on the operating temperature: applying intermediate potential offset at high temperatures to reduce leakage, and reducing or eliminating this offset at low temperatures where leakage is naturally lower. This dynamic adaptation optimizes both leakage reduction effectiveness and test time across different temperature ranges.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables rapid stabilization of the memory cell potential, reducing testing time and maintaining data retention capabilities across various temperatures, thereby improving the efficiency of semiconductor memory devices.
Implementation Method 1
a first potential adjustment part provided between the first source and a first end portion of the memory cell; and a second potential adjustment part provided between the second source and the first end portion of the memory cell
Data Source
AI summary
A semiconductor device includes a memory unit having a memory cell driven by a voltage applied from power supply lines VSS and VDD, and a memory unit potential controller for adjusting the potential of the voltage applied to the memory cell. The memory unit potential controller includes a first potential adjustment part provided between the power supply lines VSS and ARVSS, and a second potential adjustment part provided between the power supply lines VDD and ARVSS. Further, the memory unit potential controller adjusts the potential of the power supply line ARVSS based on a first current supplied between the power supply line VSS and a first end portion of the memory cell through the first potential adjustment part, and adjusts a second current supplied between the power supply lines VDD and ARVSS through the second potential adjustment part, in order to rapidly stabilize the potential applied to the memory cell.