Memory Cell Power Routing Across Metal Layers to Reduce IR Drop
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Solution Overview
Problem
The challenge in semiconductor fabrication is the significant voltage drop (IR drop) across metal stripes in integrated circuits, which affects the performance and efficiency of integrated circuits, particularly in memory devices, due to the increasing density and shrinking form factor of semiconductor devices.
Innovation Solution
The solution involves using asymmetric metal layers for power routing, where one metal layer provides a larger power stripe for a first voltage source and another metal layer provides a second voltage source, with wider power stripes in different layers to reduce the IR drop, and sharing power stripes between adjacent cells to increase the total area and improve connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If metal stripe width is reduced to increase device density, then device density is improved, but voltage drop (IR drop) increases
Solution Approach 1:
The patent transitions from two-dimensional power distribution to three-dimensional power distribution by utilizing multiple metal layers. Power stripes are distributed across different vertical layers (e.g., first metal layer, second metal layer, third metal layer), allowing power delivery from multiple directions and reducing the burden on any single stripe width while maintaining low IR drop.
Solution Approach 2:
The power distribution network is segmented into multiple independent power stripes across different metal layers. Each layer contains separate power stripes that can be independently optimized, allowing the system to achieve low IR drop through collective contribution of multiple segments rather than relying on a single wide stripe.
2Loss of energy
If metal stripe width is increased to reduce IR drop, then voltage drop is reduced, but device density decreases
Solution Approach 1:
Instead of increasing stripe width in the horizontal plane, the patent extends power distribution into the vertical dimension by using multiple metal layers. This allows the effective power delivery area to increase without reducing device density in the planar layout.
Solution Approach 2:
Multiple power stripes from different metal layers are merged to form a collective power distribution system. The combined effect of these stripes achieves the low IR drop that would require excessively wide single stripes, while preserving high device density.
3Productivity
If asymmetric metal layers are used for power routing, then power distribution efficiency is improved, but manufacturing complexity increases
Solution Approach 1:
The patent employs asymmetric metal layer configurations where different metal layers have different numbers, widths, and arrangements of power stripes. For example, the first metal layer may have a different power stripe configuration than the second metal layer, allowing optimization for specific power delivery requirements while maintaining manufacturability through systematic design rules.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the IR drop across power stripes, enhancing the operation and performance of integrated circuits by increasing the area of power stripes and improving connectivity, thereby supporting higher performance and efficiency in memory devices.
Implementation Method 1
a first metal stripe in the first metal layer is configured to connect to a first voltage source to provide a first voltage signal... a second metal stripe in the third metal layer is configured to connect to a second voltage source to provide a second voltage signal
Implementation Method 2
The challenge in semiconductor fabrication is the significant voltage drop (IR drop) across metal stripes in integrated circuits... wider power stripes in different layers to reduce the IR drop
Data Source
AI summary
Various memory cell structures and power routings for one or more cells in an integrated circuit are disclosed. In one embodiment, different metal layers are used for power stripes that are operable to connect to voltage sources to supply different voltage signals, which allows some or all of the power stripes to have a larger width. Additionally or alternatively, fewer metal stripes are used for signals in a metal layer to allow the power stripe in that metal layer to have a larger width. The larger width(s) in turn increases the total area of the power stripe(s) to reduce the IR drop across the power stripe. The various power routings include connecting metal pillars in one metal layer to a power stripe in another metal layer, and extending a metal stripe in one metal layer to provide additional connections to a power stripe in another metal layer.