Memory Cell Preconditioning for Imprint Error Reduction

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Solution Overview

Problem

Conventional memory cell technologies face issues with imprint effects during storage periods, where one memory state becomes favored, leading to errors during readout operations due to shifts in coercive fields and residual polarizations in remanent-polarizable layers, especially at elevated temperatures.

Innovation Solution

A conditioned writing scheme is implemented, which includes supplying a precondition signal to restore the memory cell to a predefined condition before writing, ensuring all memory states remain equally stable, thereby preventing imprint-related errors and maintaining accurate readout operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Duration of action of stationary object

If memory cells are stored for extended periods, then data retention is achieved, but imprint effects cause one memory state to become favored leading to readout errors

Engineering Contradiction:
Improvestorage periodVSAvoidreadout accuracy
Core Design Contradiction:
Duration of action of stationary objectVSReliability

Solution Approach 1:

A precondition signal is applied to the memory cell before the write operation to restore the memory cell to a predefined condition. This preliminary action ensures that the memory cell is in a stable state with equal stability for both memory states, preventing imprint effects from causing readout errors during extended storage periods.

Inventive Principle:
Principle #10Preliminary action

2Temperature

If elevated temperatures are present during storage, then thermal energy is available, but coercive fields and residual polarizations shift causing memory state instability

Engineering Contradiction:
Improveelevated temperatureVSAvoidmemory state stability
Core Design Contradiction:
TemperatureVSStability of the object's composition

Solution Approach 1:

The precondition signal is applied before writing to counteract the effects of elevated temperatures on coercive fields and residual polarizations. This restores the memory cell to a predefined condition where both memory states remain equally stable even at elevated temperatures, preventing thermal-induced instability.

Inventive Principle:
Principle #10Preliminary action

3Device complexity

If conventional writing schemes are used, then write operations are simple, but imprint effects accumulate leading to increased read failures

Engineering Contradiction:
Improvewriting scheme complexityVSAvoidread failure rate
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The writing scheme includes a precondition signal applied before the write operation. This additional step restores the memory cell to a predefined condition, preventing imprint effects from accumulating and reducing read failures, while maintaining relatively simple overall system architecture.

Inventive Principle:
Principle #10Preliminary action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The conditioned writing scheme effectively reduces read failures by restoring the memory cell's predefined state, ensuring stable polarization and accurate data storage across varying temperatures, thus enhancing the reliability of memory cell operations.

Implementation Method 1

shifts in coercive fields and residual polarizations in remanent-polarizable layers

Methodology Applied
Scientific EffectResidual polarization: Polarisation

Implementation Method 2

imprint effects during storage periods, where one memory state becomes favored

Methodology Applied
Scientific EffectImprint effect: Hysteresis

Data Source

PatentUS11049541B2Memory cell arrangement and methods thereof
Publication Date: 2021.06.29 FERROELECTRIC MEMORY GMBH
  • US11049541B2 patent drawing
  • US11049541B2 patent drawing
  • US11049541B2 patent drawing

AI summary

A memory cell arrangement is provided that may include: a control circuit configured to supply a precondition signal and one of at least two write signals to a memory cell of the memory cell arrangement, the memory cell including a field-effect transistor structure and a remanent-polarizable layer, wherein the precondition signal is configured to bring the memory cell from an actual condition into a predefined condition, wherein the predefined condition is associated with a predefined threshold voltage of the field-effect transistor structure of the memory cell, and wherein the at least two write signals are configured to write the memory cell selectively into a first memory state or into a second memory state.