Neural Network Memory Cell Circuit for Low-Power Product-Sum Computing
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Solution Overview
Problem
Existing semiconductor devices require large circuit areas and high power consumption to perform multi-bit arithmetic operations necessary for neural networks, limiting their scalability and efficiency.
Innovation Solution
A semiconductor device incorporating an offset circuit with constant current circuits, transistors, capacitors, and a current mirror circuit to perform product-sum operations efficiently, using metal oxide transistors to reduce leakage current and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If digital circuits are used to perform multi-bit arithmetic operations for neural networks, then calculation accuracy is improved, but chip area increases
Solution Approach 1:
The patent replaces digital circuit arithmetic operations with analog circuit operations. Specifically, it uses operational amplifiers to perform product-sum operations (multiplication and addition) through analog signal processing, where the output signal is proportional to the sum of products of input signals and weight coefficients. This substitution of mechanical/digital computation with analog computation significantly reduces the chip area required while maintaining calculation accuracy for neural network operations.
2Measurement precision
If digital circuits are used to perform multi-bit arithmetic operations for neural networks, then calculation accuracy is improved, but power consumption increases
Solution Approach 1:
The patent replaces energy-intensive digital circuit operations with low-power analog circuit operations. The operational amplifier-based analog computation performs product-sum operations continuously with minimal power consumption, avoiding the repeated switching and regeneration of digital signals that consume significant power. This is particularly beneficial for neural network operations where the same weight coefficients are repeatedly applied to different input signals.
3Ease of manufacture
If conventional transistors are used in the circuit, then ease of manufacture is improved, but leakage current increases and power consumption increases
Solution Approach 1:
The patent employs transistors with oxide semiconductor layers (such as IGZO - indium gallium zinc oxide) as the channel formation region. These oxide semiconductor transistors exhibit extremely low off-state current characteristics due to the wide bandgap of oxide semiconductors, reducing leakage current by several orders of magnitude compared to conventional silicon-based transistors. The oxide semiconductor layer can be deposited using sputtering or other conventional semiconductor manufacturing techniques, maintaining ease of manufacture while dramatically improving power efficiency.
Data Source
AI summary
A semiconductor device capable of performing product-sum operation is provided. The semiconductor device includes a first memory cell, a second memory cell, and an offset circuit. The semiconductor device retains first analog data and reference analog data in the first memory cell and the second memory cell, respectively. A potential corresponding to second analog data is applied to each of them as a selection signal, whereby current depending on the sum of products of the first analog data and the second analog data is obtained. The offset circuit includes a constant current circuit comprising a transistor and a capacitor. A first terminal of the transistor is electrically connected to a first gate of the transistor and a first terminal of the capacitor. A second gate of the transistor is electrically connected to a second terminal of the capacitor. A voltage between the first terminal and the second gate of the transistor is held in the capacitor, whereby a change in source-drain current of the transistor can be suppressed.