Memory Cell Program Erase Parameter Adjustment
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Solution Overview
Problem
Programming in the single bit per cell (SLC) mode of memory devices causes significant damage to memory cells, leading to reduced endurance and an unfavorable cycle ratio compared to multi-level cell (MLC) mode, due to the formation of traps in the tunnel oxide layer, which affects the memory device's performance and longevity.
Innovation Solution
The approach involves modifying program and erase parameters based on the number of program-erase cycles, reducing stress on memory cells by adjusting program-verify voltage and erase-verify voltage, and reverting to default levels when cycles exceed a threshold, thereby reducing damage and extending the memory device's lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If programming is performed in SLC mode with default parameters, then programming speed is maintained, but memory cell damage increases and endurance decreases
Solution Approach 1:
The patent applies dynamics by making the program and erase parameters adjustable rather than fixed. The control circuit dynamically selects between first parameters (for low cycle counts) and second parameters (for high cycle counts) based on the current program-erase cycle count, allowing the system to adapt to the memory cell's wear state and optimize between speed and reliability at different operational stages
Solution Approach 2:
The patent directly implements parameter changes by modifying program parameters (such as program voltage levels, program pulse widths) and erase parameters (such as erase voltage levels, erase pulse widths) based on the program-erase cycle count. This allows the system to use more aggressive parameters when cells are fresh and slower parameters when cells are worn, resolving the contradiction between programming speed and cell endurance
2Productivity
If programming is performed in SLC mode with aggressive parameters, then programming speed is improved, but the cycle ratio between SLC and MLC mode becomes unfavorable
Solution Approach 1:
The system dynamically adjusts programming parameters based on the program-erase cycle count, transitioning from aggressive first parameters to conservative second parameters as cycles increase. This dynamic adaptation maintains high productivity early in the device lifecycle while extending overall device lifespan by reducing stress in later stages
Solution Approach 2:
The patent implements periodic action by changing the programming approach at different stages of the memory cell's lifecycle. The control circuit periodically evaluates the program-erase cycle count and switches between different parameter sets, creating a rhythm of aggressive programming followed by conservative programming that balances productivity and lifespan
3Reliability
If stress on memory cells is reduced during programming and erasing, then endurance is improved, but programming and erasing speeds may decrease
Solution Approach 1:
The patent resolves this contradiction through dynamic parameter selection. The control circuit chooses between first parameters (faster but more stressful) and second parameters (slower but less stressful) based on the current program-erase cycle count, ensuring that speed is maximized when cells can tolerate it while endurance is protected when cells are vulnerable
Data Source
AI summary
Apparatuses and techniques are described for modifying program and erase parameters in a memory device in which memory cells can be operated in a single bit per cell (SLC) mode or a multiple bits per cell mode. In one approach, the stress on a set of memory cells in an SLC mode is reduced during programming and erasing when the number of program-erase cycles for the block in the SLC mode is below a threshold. For example, during programming, the program-verify voltage and program voltages can be reduced to provide a shallower than normal programming. During erasing, the erase-verify voltage can be increased while the erase voltages can be reduced to provide a shallower than normal erase. When the number of program-erase cycles for the block in the SLC mode is above the threshold, the program and erase parameters revert to a default levels.