Two-Step Memory Cell Programming for 3D NAND Reliability
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Solution Overview
Problem
The scaling of planar memory cells in memory devices faces challenges due to process technology limitations and reliability issues, particularly in achieving high storage density and maintaining programming reliability in 3D NAND flash memory architectures.
Innovation Solution
A two-step programming method is introduced, where a memory cell is first programmed from an erased state into an intermediate state, and then from the intermediate state into a target state using an incremental step pulse programming (ISPP) scheme. This method involves providing a programming voltage signal to a word line and a bias voltage to a bit line, with the amplitude of the bias voltage configured according to the target or intermediate state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the distance between adjacent layers of memory cells is reduced to increase storage density, then storage density per unit area is improved, but initial threshold voltage shift and word line interference worsen
Solution Approach 1:
The programming process is segmented into two distinct steps: a first programming operation that programs memory cells into an intermediate state, and a second programming operation that programs from the intermediate state to the target state. This segmentation allows different programming parameters and verification strategies to be applied at each stage, addressing the reliability issues caused by reduced layer spacing while maintaining high storage density.
Solution Approach 2:
The first programming operation performs a preliminary programming action to establish an intermediate state before the final programming to the target state. This preliminary action prepares the memory cells in a controlled manner, reducing the impact of threshold voltage shift and word line interference that occur when layers are closely spaced.
2Reliability
If verification operations are performed during programming to ensure accuracy, then programming reliability is improved, but programming time increases
Solution Approach 1:
Verification operations are performed selectively - specifically in the second programming operation after cells are programmed from the intermediate state to the target state. The first programming operation to the intermediate state may omit verification, applying partial verification action where it is most needed while reducing overall programming time.
Solution Approach 2:
The programming process uses parameter changes by applying different programming voltages and verification strategies at different stages. The first programming operation uses parameters optimized for reaching the intermediate state, while the second programming operation uses different parameters for the final transition to the target state, with verification applied only where necessary.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The two-step programming method enhances the reliability of programming memory cells by reducing the impact of initial threshold voltage shift and word line interference, while also improving programming efficiency by omitting verification operations and using a single voltage pulse in the first programming step.
Implementation Method 1
programming a memory cell in a memory device in a two-step scheme, including a first programming operation and a second programming operation. In the first programming operation, the memory cell is programmed from the erased state into an intermediate state. In the second programming operation after the first programming operation, the memory cell is programmed from the intermediate state into a target state
Data Source
AI summary
Disclosure includes systems, methods and devices to program a memory device, involving a first and a second programming operations on a memory cell of the memory device. In the first programming operation, the memory cell is programmed into an intermediate state. In the second programming operation, the memory cell is programmed from the intermediate state into a target state. The first programming operation includes providing a bias voltage to a bit line coupled to the memory cell and providing a programming voltage to a word line coupled to the memory cell. An amplitude of the bias voltage provided to the bit line depends on the intermediate state or the target state the memory cell to be programmed into. Accordingly, no verification operation need to be performed on the memory cell in the first programming operation.