Memory Cell Programming via Electrostatic Block Insulation

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Solution Overview

Problem

The increasing proximity of memory cells in modern memory devices leads to significant electrical interactions between adjacent cells, causing threshold value alterations and reduced reliability due to parasitic capacitive coupling, which is particularly problematic in multilevel memory devices where it results in widened threshold distributions and reading errors.

Innovation Solution

The method involves programming memory cells in electrostatically insulated blocks, with initial separation and redistribution of bytes into bit packages, and a staircase-like pulse sequence to minimize capacitive coupling effects, using reduced erasing and programming voltage references to compensate for threshold variations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If memory cells are placed closer together to increase integration density, then device capacity increases, but capacitive coupling between adjacent cells increases causing threshold value alterations

Engineering Contradiction:
Improveintegration densityVSAvoidthreshold value stability
Core Design Contradiction:
Quantity of substanceVSReliability

Solution Approach 1:

The memory device is divided into multiple independently controllable blocks, where each block can be programmed separately. This segmentation isolates the capacitive coupling effects within each block, preventing them from affecting the entire memory array. The block structure allows selective programming of disturbed cells while leaving other blocks unaffected.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different programming strategies are applied to different regions of the memory device. Specifically, cells that are subject to capacitive coupling (disturbed cells) are handled differently from cells that are not affected. The programming voltage and timing are locally adjusted based on the cell's position and its susceptibility to coupling effects.

Inventive Principle:
Principle #3Local quality

2Speed

If standard programming methods are used in multilevel memory devices, then programming speed is maintained, but threshold distribution widens causing reading errors

Engineering Contradiction:
Improveprogramming speedVSAvoidthreshold distribution width
Core Design Contradiction:
SpeedVSMeasurement precision

Solution Approach 1:

Before performing complete programming, a preliminary programming step is executed to establish an initial charge state in the floating gate. This preliminary action prepares the cells for the subsequent programming step, allowing the final threshold values to be achieved with better control and reduced distribution width, while maintaining overall programming speed.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The programming process is divided into periodic steps with different voltage levels and durations. Instead of applying a single continuous programming pulse, the method uses multiple discrete programming phases, including preliminary programming and complete programming steps, which are applied periodically to gradually build up the desired threshold distribution with reduced widening.

Inventive Principle:
Principle #19Periodic action

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach reduces the widening of the threshold window caused by capacitive coupling, enhancing the reliability of memory devices by minimizing the impact of adjacent cell interactions during programming, especially in multilevel devices.

Implementation Method 1

the capacitive coupling between the floating gates of adjacent cells can be considered negligible... such capacitive interaction between adjacent cells is no more negligible

Methodology Applied
Scientific EffectCapacitive coupling: Capacitance

Data Source

PatentUS7471571B2Method for programming a memory device suitable to minimize the lateral coupling effects between memory cells
Publication Date: 2008.12.30 MICRON TECHNOLOGY INC
  • US7471571B2 patent drawing
  • US7471571B2 patent drawing
  • US7471571B2 patent drawing

AI summary

A method programs a memory device that includes at least one memory cell matrix. The programming method the steps of: erasing the memory cells; soft programming the memory cells; and complete programming of a group of such memory cells each of them storing its own logic value. Advantageously, the first complete programming step of a group of such memory cells involves cells belonging to a block (A) of the matrix being electrically insulated from the rest of the matrix. A memory device suitable to implement the proposed method is also described.