Memory Cell Programming via Dual Verify and Variable Bit Line Biasing
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Solution Overview
Problem
Flash memory devices face challenges in maintaining tight threshold voltage distributions, especially in multi-level cell (MLC) memory devices, which can lead to errors due to overlapping voltage distributions, as they try to store multiple data states within a limited voltage range.
Innovation Solution
Implementing a dual level verification method and variable bit line biasing during programming pulses to adjust the programming rate of memory cells, where the bit line voltage is increased by a variable amount based on previous thresholds, allowing for more precise control over threshold voltage changes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multiple data states are stored within a limited voltage range in MLC memory devices, then storage capacity is improved, but threshold voltage distributions overlap causing reading errors
Solution Approach 1:
The patent divides the programming verification process into two distinct stages: a first program verify performed during initial programming, and a second program verify performed after additional programming pulses. This segmentation allows the system to maintain tight threshold voltage distributions by adjusting verification timing and parameters for different programming phases, thereby preventing distribution overlap while preserving multi-level storage capacity.
Solution Approach 2:
The patent dynamically adjusts the bit line voltage by a variable amount based on the determined threshold voltage from the first program verify. This dynamic adjustment optimizes the programming rate and ensures that threshold voltage distributions remain tight and separated, preventing overlap between multiple data states while maintaining high storage capacity.
2Loss of information
If programming pulses are applied to increase threshold voltage, then data storage is achieved, but threshold voltage distributions broaden causing state overlap
Solution Approach 1:
The patent implements a feedback mechanism where the result of the first program verify (determined threshold voltage) is used to dynamically adjust the bit line voltage for subsequent programming pulses. This feedback loop ensures that programming is optimized to achieve tight threshold voltage distributions, preventing broadening and overlap while maintaining accurate data storage across multiple states.
Solution Approach 2:
The patent changes the bit line voltage parameter by a variable amount based on the determined threshold voltage. This parameter adjustment optimizes the programming process to achieve tight threshold voltage distributions, ensuring that data storage is achieved without distribution broadening that would cause state overlap.
3Ease of operation
If uniform bit line voltage is applied during programming, then programming process is simple, but programming rate cannot be optimized for different threshold voltage states
Solution Approach 1:
The patent transitions from a static, uniform bit line voltage approach to a dynamic approach where the bit line voltage is adjusted by a variable amount based on the determined threshold voltage. This dynamic adjustment optimizes the programming rate for different threshold voltage states while maintaining reasonable process complexity through systematic voltage adjustment rules.
Solution Approach 2:
The patent changes the bit line voltage parameter dynamically based on programming progress and determined threshold voltage. This parameter optimization enables faster programming rates for different states without significantly complicating the overall programming process, as the adjustment follows a systematic approach based on verify results.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in tighter threshold voltage distributions, reducing errors in reading data states and ensuring accurate storage of multiple bits per cell by optimizing the programming process.
Implementation Method 1
Each programming pulse increases a charge level on a charge trapping material (e.g., floating gate) of the target memory cell, thereby increasing the cell's threshold voltage Vt
Data Source
AI summary
Memory devices and methods for operating a memory cell are disclosed, such as a method that uses two program verify levels (e.g., low program verify level and program verify level) to determine how a data line voltage should be increased. A threshold voltage of a memory cell that has been biased with a programming voltage is determined and its relationship with the two program verify levels is determined. If the threshold voltage is less than the low program verify level, the data line can be biased at a ground voltage (e.g., 0V) for a subsequent programming pulse. If the threshold voltage is greater than the program verify level, the data line can be biased at an inhibit voltage for a subsequent programming pulse. If the threshold voltage is between the two program verify levels, the data line voltage can be increased for each subsequent programming pulse in which the threshold voltage is between the two program verify levels.