Multilevel Memory Cell Initialization via Programming
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Solution Overview
Problem
Existing memory technologies face challenges in efficiently programming and erasing multilevel memory cells, particularly in nonvolatile semiconductor memory systems, where the block-level erase-verify operation is not feasible in NOR type memory arrays, leading to issues with data retention and electrical stress on memory cells.
Innovation Solution
A two-step method is introduced, where memory cells are initialized by programming to a state higher than the lowest state instead of over-erasing, allowing for faster programming and verification, and the threshold voltage is adjusted based on user data using techniques like channel hot-electron injection and Fowler-Nordheim tunneling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block-level erase-verify operation is performed in NOR type memory arrays, then data retention is improved, but the operation is not feasible leading to electrical stress on memory cells
Solution Approach 1:
The patent divides the memory array into multiple banks, allowing parallel erase operations to be performed on different banks simultaneously. This segmentation enables the erase-verify operation to be implemented in NOR type memory arrays by organizing memory cells into manageable units that can be processed independently, reducing electrical stress while maintaining data retention reliability.
Solution Approach 2:
The patent implements dynamic voltage adjustment during erase operations, adapting the erase voltage based on the specific state of memory cells and the progress of the erase operation. This dynamic approach optimizes the erase process to achieve reliable data retention while minimizing unnecessary electrical stress on memory cells that have already been adequately erased.
2Reliability
If over-erasing is performed to initialize memory cells, then data retention is improved, but programming time increases and electrical stress increases
Solution Approach 1:
The patent replaces the traditional over-erasing mechanism with a programming-based initialization approach. Instead of using high-voltage erase operations to initialize memory cells, the system uses controlled programming operations that set memory cells to known states with lower voltage stress, thereby reducing both programming time and electrical stress while maintaining adequate data retention.
Solution Approach 2:
The patent changes the operational parameters of memory cell initialization by using programming voltage profiles instead of erase voltage profiles. This parameter change allows memory cells to be initialized to valid states without the excessive voltage application characteristic of over-erasing, thus reducing programming time and electrical stress while preserving data retention through proper state establishment.
3Reliability
If traditional erase methods are used, then memory cells are initialized, but the process is slow and causes electrical stress
Solution Approach 1:
The patent segments the memory array into multiple banks that can be initialized in parallel. By dividing the large memory array into smaller, independently initializable units, the overall initialization process is accelerated while maintaining reliable memory cell state establishment, and the distributed approach reduces peak electrical stress on any single memory cell.
Solution Approach 2:
The patent employs dynamic initialization strategies that adapt the initialization process based on memory cell states and operational requirements. This dynamic approach allows faster initialization speeds by using optimized voltage profiles and timing sequences, while dynamically monitoring and adjusting parameters prevents excessive electrical stress on memory cells.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach eliminates the need for over-erasing, reduces electrical stress, and enables faster data operations by allowing block-level program-verify and page-level erase-verify operations, improving data throughput and retention.
Implementation Method 1
The program module programs the nonvolatile multilevel memory cell with user data by injecting hot electrons into the floating gate
Implementation Method 2
The program module programs the nonvolatile multilevel memory cell by inducing Fowler-Nordheim tunneling of electrons into the floating gate
Implementation Method 3
The erase module erases the nonvolatile multilevel memory cell by inducing band-to-band tunneling and hot-hole injection
Implementation Method 4
The erase module erases the nonvolatile multilevel memory cell by inducing band-to-band tunneling and hot-hole injection
Data Source
AI summary
A system includes an input that receives a control signal and a program module that initializes a nonvolatile multilevel memory cell based on the control signal. The program module initializes the nonvolatile multilevel memory cell by programming the nonvolatile multilevel memory cell to one of S states of the nonvolatile multilevel memory cell, where S is an integer greater than 1. The one of the S states is different than a lowest one of the S states.