Multi-State Memory Cell Programming Pattern
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Solution Overview
Problem
Current NAND technology faces challenges in programming multi-state memory cells, particularly for 3 state and 6 state cells, which require complex calculation circuits to store 0.5 bit increments, and is affected by the Yupin effect, where data disturbance occurs due to field effect coupling between adjacent cells.
Innovation Solution
A non-volatile memory system with a method that programs memory cells in a specific pattern, alternating between even and odd memory cells on word lines to minimize data disturbance and optimize programming speed, allowing for efficient storage of 0.5 bit increments without the need for complex book-keeping logic.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-state memory cells (3 state, 6 state) are programmed to store 0.5 bit increments, then storage capacity is improved, but complex calculation circuits are required for book-keeping
Solution Approach 1:
The memory array is divided into alternating even and odd memory cells organized in separate columns. Even memory cells are programmed first, followed by odd memory cells. This segmentation allows independent programming sequences that simplify the book-keeping logic by treating half-cell increments as complete operations within each column type.
Solution Approach 2:
Even memory cells are programmed in advance before odd memory cells are programmed. This preliminary action establishes a known state for the first set of cells, allowing the programming system to track and manage charge levels more easily by completing full programming cycles in sequential batches rather than interleaving them.
2Productivity
If programming speed is optimized, then productivity is improved, but Yupin effect (data disturbance) increases due to field effect coupling between adjacent cells
Solution Approach 1:
The memory array is divided into alternating even and odd memory cells organized in separate columns. Even memory cells are programmed first, followed by odd memory cells. This segmentation allows independent programming sequences that minimize interference between simultaneously programmed cells, reducing the Yupin effect while maintaining high programming speed through parallel processing of each column type.
3Quantity of substance
If memory cell size is decreased to increase density, then quantity of memory cells is improved, but Yupin effect increases due to increased field effect coupling between adjacent cells
Solution Approach 1:
The memory array is divided into alternating even and odd memory cells organized in separate columns. Even memory cells are programmed first, followed by odd memory cells. This segmentation allows independent programming sequences that minimize interference between simultaneously programmed cells, reducing the Yupin effect while maintaining high programming speed through parallel processing of each column type.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient storage of data in 0.5 bit increments with optimized programming speed and reduced Yupin effect, eliminating the need for complex calculation circuits and maintaining simple logic in high-density multi-state memory cells.
Implementation Method 1
One source of these disturbs is the field effect coupling between adjacent floating gates as described in U.S. Pat. No. 5,867,429 of Jian Chen and Yupin Fong
Data Source
AI summary
A method for programming a non-volatile memory system. The method includes programming a first non-volatile storage element on a first word line and a first NAND string to store “n” bits of data. A second non-volatile storage element on the first word line and a second NAND string is programmed to store n+1 bits of data. The second non-volatile storage element is a neighbor to the first non-volatile storage element. A third non-volatile storage element on a second word line and the second NAND string is programmed to store n bits of data. The third non-volatile storage element is a neighbor to the second non-volatile storage element. A fourth non-volatile storage element on the second word line and the first NAND string is programmed to store n+1 bits of data.