Memory Cell Programming Verification Error Detection
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Solution Overview
Problem
Existing programming verification processes in memory devices may incorrectly program memory cells to higher states or fail to detect programming errors, leading to undetected errors and incorrect reporting of successful programming operations.
Innovation Solution
Implementing a Program and Verify (P&V) process that includes a read-after-write command to compare stored data with original data, assessing the number of memory cells exceeding verification thresholds, and measuring programming times to identify and report programming errors, and prevent double programming.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional P&V process is used for programming memory cells, then programming speed is improved, but programming accuracy deteriorates leading to undetected errors
Solution Approach 1:
The patent implements a read-after-write verification step immediately following the programming operation. This preliminary verification action detects programming errors before they propagate to subsequent operations, thereby maintaining programming speed while improving accuracy by catching errors in the verification stage rather than allowing them to persist.
Solution Approach 2:
The patent establishes a feedback mechanism where the read-after-write operation provides information about programming success or failure. This feedback loop allows the system to detect when memory cells have been incorrectly programmed to higher states and report errors accordingly, resolving the contradiction between speed and accuracy by adding verification without significantly impacting overall programming throughput.
2Measurement precision
If verification thresholds are lowered to detect more errors, then measurement precision is improved, but false positive errors increase
Solution Approach 1:
The patent dynamically adjusts verification thresholds based on the specific programming operation and memory cell state. By changing the threshold parameters adaptively rather than using fixed low thresholds, the system achieves high error detection precision while avoiding false positives that would occur with consistently low thresholds across all operations.
Solution Approach 2:
The patent applies different verification thresholds to different memory cells or cell groups based on their specific characteristics and programming history. This localized approach allows each cell to be verified with the appropriate threshold level, improving overall detection precision without causing false positives in cells that don't require such sensitive verification.
3Reliability
If read-after-write verification is implemented, then programming accuracy is improved, but processing time increases
Solution Approach 1:
The patent implements read-after-write verification for all programming operations, which may seem excessive, but this comprehensive approach ensures that programming accuracy is maintained without requiring complex conditional logic to determine which cells need verification. The uniform application of verification simplifies the control logic and reduces overhead time compared to selective verification approaches.
Solution Approach 2:
The patent combines the verification process with the existing programming operation flow by integrating read-after-write into the standard programming sequence. This merging of programming and verification into a unified process reduces the overall time loss compared to treating them as separate, sequential operations, thereby improving accuracy while minimizing the impact on processing time.
Data Source
AI summary
A method for data storage includes receiving in a memory device data for storage in a group of memory cells. The data is stored in the group by performing a Program and Verify (P&V) process, which applies to the memory cells in the group a sequence of programming pulses and compares respective analog values of the memory cells in the group to respective verification thresholds. Immediately following successful completion of the P&V process, a mismatch between the stored data and the received data is detected in the memory device. An error in storage of the data is reported responsively to the mismatch.