Memory Cell Programming Voltage Arrangement
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Solution Overview
Problem
Conventional non-volatile memory cells experience over-programming issues due to cross interference between stored bits, leading to a looser voltage threshold distribution curve and reduced device reliability.
Innovation Solution
A method of programming memory cells involves applying a first voltage arrangement for programming a first region and a second, lower voltage arrangement for programming a second region, with the second gate voltage being less than the first, thereby reducing the programming efficiency of the second bit and achieving a tighter voltage threshold distribution curve.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional voltage arrangement is used for programming both bits in a 2 bits/cell memory cell, then the programming operation can be completed, but the existing bit affects the programming efficiency of another bit leading to over-programming and a looser Vt distribution curve
Solution Approach 1:
The patent applies different voltage arrangements for programming different regions (first bit and second bit) within the same memory cell. Specifically, when programming the second bit, a second voltage arrangement with a second gate voltage is used that is lower than the first gate voltage used for programming the first bit. This local differentiation in voltage application prevents the already-programmed first bit from causing over-programming of the second bit, thereby tightening the Vt distribution curve and improving manufacturing precision without compromising device reliability.
2Device complexity
If the same gate voltage is applied for programming both first and second bits, then the programming process is simplified, but cross interference between bits increases causing over-programming
Solution Approach 1:
The patent changes the voltage parameter (gate voltage) based on which bit is being programmed. A first voltage arrangement with a first gate voltage is used for programming the first bit, while a second voltage arrangement with a second gate voltage (lower than the first) is used for programming the second bit. This parameter adjustment reduces the harmful cross interference effect while maintaining a relatively simple programming process structure, thus resolving the contradiction between process complexity and cross interference.
3Productivity
If high gate voltage is used for programming the second bit to ensure programming efficiency, then programming speed is improved, but the existing first bit causes over-programming and loosens the Vt distribution
Solution Approach 1:
The patent implements a dynamic voltage adjustment strategy where the gate voltage level is adapted based on the programming sequence. When programming the second bit, the system dynamically selects a lower second gate voltage compared to the first gate voltage used for the first bit. This dynamic adjustment ensures that programming efficiency is maintained while preventing over-programming caused by the interaction with the already-programmed first bit, thereby tightening the Vt distribution curve.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces over-programming and results in a tighter voltage threshold distribution curve, enhancing device reliability by minimizing the impact of stored bits on programming efficiency.
Implementation Method 1
hot electrons generated in a channel region are injected into the nitride layer 110 adjacent to a side of the drain 106 so as to store a bit 116
Data Source
AI summary
A method of programming a memory cell is described. The memory cell includes a gate with a charge trapping layer isolated from a substrate for storing data with a first region and a second region separated from the first region. The method of programming the memory cell includes applying a first voltage arrangement with a first gate voltage for programming the first region and applying a second voltage arrangement with a second gate voltage for programming the second region. The first gate voltage is greater than the second gate voltage.