Memory Cell With Protruding Patterned Layer Preventing Silicide Shorts
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Solution Overview
Problem
Conventional SONOS memory cells face increased errors and reliability issues due to reduced size of the charge trapping layer and fewer stored electrons, leading to performance degradation as semiconductor devices shrink.
Innovation Solution
A memory cell design featuring a patterned material layer with a vertical and horizontal portion, where the vertical portion protrudes over the selection gate, preventing continuous silicide formation between the control and selection gates, thus avoiding shorts and enhancing performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the charge trapping layer size is reduced to shrink device size, then device miniaturization is achieved, but the number of stored electrons decreases leading to increased errors and reduced reliability
Solution Approach 1:
The patent introduces a third dimension by forming the patterned material layer with a vertical portion that protrudes above the selection gate. This vertical extension increases the effective charge trapping volume without expanding the lateral device footprint, thereby maintaining miniaturization while improving reliability through increased electron storage capacity.
Solution Approach 2:
The patterned material layer is segmented into a vertical portion and a horizontal portion. The vertical portion is positioned to protrude over the selection gate, creating distinct functional regions that prevent silicide formation between gates while maintaining adequate charge trapping capacity.
2Ease of manufacture
If conventional silicide formation is used, then manufacturing simplicity is maintained, but silicide shorts between control gate and selection gate occur degrading performance
Solution Approach 1:
The patterned material layer is formed with a vertical portion protruding above the selection gate before silicide formation. This preliminary structural arrangement prevents silicide shorts by creating a physical barrier that blocks continuous silicide formation between the control gate and selection gate, while still allowing standard silicide processing to be used.
Data Source
AI summary
The present invention provides a memory cell, which includes a substrate, a gate dielectric layer, a patterned material layer, a selection gate and a control gate. The gate dielectric layer is disposed on the substrate. The patterned material layer is disposed on the substrate, wherein the patterned material layer comprises a vertical portion and a horizontal portion. The selection gate is disposed on the gate dielectric layer and atone side of the vertical portion of the patterned material layer. The control gate is disposed on the horizontal portion of the patterned material layer and at another side of the vertical portion, wherein the vertical portion protrudes over a top of the selection gate. The present invention further provides another embodiment of a memory cell and manufacturing methods thereof.