Memory Cell Read Circuit Glitch Prevention via Valid Bit Latching

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Solution Overview

Problem

Conventional memory cell arrangements experience glitches due to signal races in combinatorial circuit elements during fast read operations, leading to invalid data reads on the data bus.

Innovation Solution

Implementing a memory cell arrangement with a valid bit mechanism that gates the read data only after it is latched, using a valid bit signal to enable or disable the memory cell sense amplifier circuit, thereby preventing glitches by ensuring the memory cell content is valid before being provided on the data bus.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If combinatorial circuit elements are used to gate read data, then data reading speed can be increased, but glitches occur due to signal races

Engineering Contradiction:

Improvedata reading speedVSAvoiddata validity

Core Design Contradiction:

SpeedVSReliability

Solution Approach 1:

The valid bit is latched before the data read operation completes. This preliminary latching of the valid bit status allows the system to determine data validity in advance, enabling the gating circuit to prevent glitches from reaching the data bus before the actual data read completes, thus resolving the contradiction between speed and reliability

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

A valid bit signal is introduced as an intermediary between the data read path and the data bus. This valid bit acts as a mediator that controls the gating circuit, allowing the system to separate the data reading operation from the data output, thereby preventing signal races from causing glitches while maintaining high read speeds

Inventive Principle:

Principle #24Intermediary (Mediator)

2Reliability

If valid bit gating is implemented after latching, then glitches are prevented, but additional circuit elements are required

Engineering Contradiction:

Improveglitch preventionVSAvoidcircuit elements

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The valid bit latching function and the data gating function are merged into a single coordinated operation. The valid bit is latched and used to control the gating circuit in an integrated manner, rather than using separate independent circuits. This merging reduces the overall circuit complexity while still providing reliable glitch prevention

Inventive Principle:

Principle #5Merging (Combining)

Solution Approach 2:

The valid bit mechanism serves multiple functions: it indicates data validity status, controls the gating circuit, and prevents glitches. By making the valid bit multi-functional, the system reduces the need for additional dedicated circuit elements, thereby limiting the increase in device complexity while achieving reliable glitch prevention

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS7826280B2Integrated circuit and method for reading the content of a memory cell

Publication Date: 2010.11.02 SAMSUNG ELECTRONICS CO LTD

AI summary

In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, a read circuit configured to read the memory cell, wherein the read circuit includes an output holding circuit configured to hold a memory cell content signal read from the memory cell, and an enable circuit configured to provide the memory cell content signal at an output of the read circuit only in case the memory cell fulfills a predefined criterion.