Semiconductor Memory Cell Read Operation Optimization
Solution Overview
Problem
Current semiconductor memory devices require lengthy reading operations due to the need for multiple threshold voltages in multi-level cells, leading to increased read time and potential errors from overlapping data distributions.
Innovation Solution
A semiconductor memory device that includes a memory cell, a control signal generation unit, an information storage unit, and an output unit to change the cell state and store variation status information, allowing for reduced read time by detecting the moment when the cell state changes and outputting data based on this information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If multi-level cell is used to store more than one bit data in one memory cell, then storage capacity is improved, but read time increases due to requiring multiple threshold voltage readings
Solution Approach 1:
The patent segments the reading process into multiple sequential stages, each stage reading one bit of data by applying a specific threshold voltage. Instead of performing multiple readings simultaneously or using complex parallel circuits, the method divides the multi-bit reading task into separate time segments, where each segment handles one threshold voltage comparison. This segmentation allows multi-level cells to store multiple bits while reading them out sequentially, reducing the complexity of simultaneous multi-threshold voltage application circuits.
Solution Approach 2:
The patent applies preliminary actions by pre-charging bit lines to specific voltage levels before reading operations and pre-positioning control signals for each threshold voltage comparison. The bit lines are pre-charged to reference voltages that correspond to the threshold voltages of the memory cells, and control signals for selecting which threshold voltage to apply are prepared in advance. This preliminary preparation reduces the actual read time by eliminating setup delays during the critical reading phase.
2Measurement precision
If multiple threshold voltages are used to distinguish data distributions, then data accuracy is improved, but the number of reading operations increases
Solution Approach 1:
The patent employs periodic action by applying threshold voltages in a systematic sequence, where each threshold voltage is applied for a predetermined time period followed by a sensing phase. The reading operation cycles through multiple threshold voltages (Vth1, Vth2, Vth3, etc.) in a repeating pattern, with each cycle reading one bit of data. This periodic application of threshold voltages allows accurate distinction between overlapping data distributions while maintaining a regular, predictable reading rhythm that optimizes productivity.
Solution Approach 2:
The patent ensures continuity of useful action by overlapping the sensing phase of one threshold voltage reading with the preparation phase of the next threshold voltage application. While one bit is being sensed, the next threshold voltage is being prepared and control signals are being readied. This continuous pipeline operation eliminates idle time between reading operations, maintaining high productivity while still performing multiple threshold voltage comparisons for accurate data retrieval.
3Quantity of substance
If data distributions are made narrower through fabrication progress, then storage density is improved, but overlap between neighboring distributions increases
Solution Approach 1:
The patent applies partial or excessive action by using more threshold voltages than the minimum required to distinguish data levels. For example, to read 2 bits of data stored in a multi-level cell, the patent may apply 3 or more threshold voltages instead of the theoretical minimum of 2. This excessive number of threshold voltage comparisons provides redundant verification and allows the system to tolerate some overlap between data distributions by using majority voting or error correction logic to determine the final data value, thereby maintaining high reliability despite narrower data distributions.
Data Source
AI summary
A semiconductor memory device includes a memory cell suitable for having a predetermined cell state based on a data stored therein, a control signal generation unit suitable for generating a control signal for changing the cell state of the memory cell during a reading operation, an information storage unit suitable for storing a variation status information of the control signal to which a moment when the cell state of the memory cell changes is reflected, and an output unit suitable for outputting the variation status information of the control signal stored in the information storage unit as a signal corresponding to the data stored in the memory cell.