Memory Cell Reference Erase for Read Accuracy
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory arrays experience cycling degradation due to multiple loop operations, affecting the accuracy of reading memory cells by altering the current they provide.
Innovation Solution
A memory storage device with a memory array and a sensing amplifier circuit, where the memory array includes a memory cell and a reference cell that are erased together, and the sensing amplifier circuit compares the cell current of the memory cell with the reference current of the programmed reference cell to determine the state of the memory cell.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple loop operations are performed to write data to memory cells, then data storage capability is improved, but cycling degradation occurs affecting reading accuracy
Solution Approach 1:
The patent changes the operational parameters by performing erase operations on both the memory cell and reference cell together, then programming only the reference cell. This parameter change ensures that both cells experience the same cycling degradation while maintaining distinguishable states for accurate reading comparison.
Solution Approach 2:
The patent applies preliminary action by erasing both the memory cell and reference cell together before the programming operation. This preliminary erase operation ensures that both cells start from the same baseline state, allowing them to undergo identical cycling degradation and enabling accurate comparative reading later.
2Duration of action of moving object
If memory cells undergo cycling degradation, then writing operations can be performed, but the current provided by memory cells changes affecting reading accuracy
Solution Approach 1:
The patent changes the operational parameters by performing erase operations on both the memory cell and reference cell together, then programming only the reference cell. This parameter change ensures that both cells experience the same cycling degradation while maintaining distinguishable states for accurate reading comparison.
Solution Approach 2:
The patent uses the reference cell as a copy that mirrors the cycling degradation of the memory cell. By programming the reference cell after erasing both cells together, the reference cell becomes a degraded copy that provides a reliable baseline for comparison, enabling accurate reading despite degradation.
3Device complexity
If reference cell is not erased with memory cell, then reading comparison can be simplified, but cycling degradation levels become inconsistent affecting accuracy
Solution Approach 1:
The patent applies preliminary action by erasing both the memory cell and reference cell together before the programming operation. This preliminary erase operation ensures that both cells start from the same baseline state, allowing them to undergo identical cycling degradation and enabling accurate comparative reading later.
Solution Approach 2:
The patent changes the operational parameters by performing erase operations on both the memory cell and reference cell together, then programming only the reference cell. This parameter change ensures that both cells experience the same cycling degradation while maintaining distinguishable states for accurate reading comparison.
Data Source
AI summary
A memory storage device including a memory array and a sensing amplifier circuit is provided. The memory array includes a memory cell and a reference cell. During an erase phase, the memory cell and the reference cell are erased together. The sensing amplifier circuit is coupled to the memory array. During a reading phase, the sensing amplifier circuit compares a cell current of the memory cell with a reference current of the programmed reference cell to determine a state of the memory cell. In addition, a reading method for a memory storage device is also provided.