Memory Cell Refresh via Bit Inversion for Reliability

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Solution Overview

Problem

The miniaturization of integrated circuits (ICs) has led to stricter design and manufacturing specifications, as well as reliability challenges due to the constant inversion of stored bit values in memory cells, which can cause stress and reduce the reliability of memory devices.

Innovation Solution

A memory device architecture that stores a data word and an indicator bit in an array of bit cells, where the array is repetitively refreshed with bit inversion. This allows the original bit value of each data bit to be recovered based on the stored bit value of the corresponding data bit and the indicator bit, reducing stress on bit cells and improving reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If memory cells are miniaturized to reduce device size and power consumption, then integration density and functionality are improved, but reliability deteriorates due to constant inversion of stored bit values causing stress on memory cells

Engineering Contradiction:

Improvedevice sizeVSAvoidmemory cell reliability

Core Design Contradiction:

Volume of moving objectVSReliability

Solution Approach 1:

The patent applies preliminary action by proactively inverting bit values during refresh cycles before stress accumulates to harmful levels. The memory device periodically reads and inverts stored bit values as a preventive measure, thereby reducing cumulative stress on miniaturized memory cells and improving reliability without increasing device size.

Inventive Principle:

Principle #10Preliminary action

2Stability of the object's composition

If bit values are constantly inverted in memory cells to maintain data integrity, then data retention is improved, but stress on memory cells increases reducing reliability

Engineering Contradiction:

Improvedata integrityVSAvoidmemory cell reliability

Core Design Contradiction:

Stability of the object's compositionVSReliability

Solution Approach 1:

The patent implements periodic action by performing bit inversion only during scheduled refresh cycles rather than continuously. The memory device reads and inverts bit values at specific time intervals, maintaining data integrity while limiting the duration of stress on memory cells, thus balancing data retention with reliability.

Inventive Principle:

Principle #19Periodic action

3Stability of the object's composition

If refresh cycles are performed frequently to maintain data integrity, then data retention is improved, but energy consumption increases

Engineering Contradiction:

Improvedata retentionVSAvoidenergy consumption

Core Design Contradiction:

Stability of the object's compositionVSUse of energy by moving object

Solution Approach 1:

The patent ensures continuity of useful action by maintaining persistent indicator bits that track inversion states across refresh cycles. This allows the memory device to perform refresh operations more efficiently by leveraging the continuous presence of indicator information, reducing the frequency or duration of full refresh operations and thereby lowering energy consumption while maintaining data retention.

Inventive Principle:

Principle #20Continuity of useful action

Data Source

PatentUS20250182809A1Method of and apparatus for refreshing memory devices

Publication Date: 2025.06.05 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

An integrated circuit includes an array of word lines, and an array of memory cells configured to receive selection signals from the array of word lines. Each memory cell in the array of memory cells is connected to one or more data lines in a set of data lines. The integrated circuit also includes a read-write driver configured to store into the selected memory cell a second bit value which is a bit inversion of the stored bit value.