Memory Cell Repair Using Redundancy for Longer Refresh Periods
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Solution Overview
Problem
Semiconductor memory cells may degrade due to defects or physical damage, necessitating a repair method to maintain data integrity and improve performance.
Innovation Solution
A memory system with a redundancy memory cell group and repair circuit that identifies and repairs weak memory cells using redundancy cells, ensuring all cells meet a minimum retention time threshold, thereby extending the refresh period and increasing data bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If refresh operation is performed on all memory cells, then data integrity is maintained, but unnecessary refresh operations increase power consumption and reduce productivity
Solution Approach 1:
The patent applies local quality by differentiating refresh operations based on individual memory cell characteristics. Instead of uniformly refreshing all memory cells, the system identifies weak cells with degraded retention times and applies refresh operations selectively to only those cells that need it, while strong cells are excluded from unnecessary refresh cycles.
Solution Approach 2:
The patent implements preliminary action by performing retention time measurement and weak cell identification before the refresh operation. The test circuit measures retention times of memory cells in advance, and the repair circuit pre-identifies weak cells that require refresh, allowing the refresh controller to optimize the refresh schedule before actual refresh operations begin.
2Reliability
If refresh period is reduced to maintain data integrity at higher temperatures, then reliability improves, but productivity decreases due to more frequent refresh operations
Solution Approach 1:
The patent applies parameter changes by adjusting the refresh period dynamically based on temperature conditions and memory cell characteristics. The system measures retention times at different temperatures and modifies the refresh period parameter accordingly, extending the refresh period for strong cells even at higher temperatures while maintaining appropriate refresh frequencies for weak cells.
3Duration of action of moving object
If retention time of memory cells is increased through repair operations, then refresh period can be extended, but device complexity increases due to test and repair circuits
Solution Approach 1:
The patent applies universality by designing the test circuit and repair circuit to serve multiple functions. The test circuit not only measures retention times but also identifies weak cells for repair. The repair circuit performs both repair operations and verification of repaired cells. These circuits are integrated into the existing memory architecture and can be controlled through standard control signals, reducing the need for separate dedicated circuits.
Data Source
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AI summary
A memory system includes a memory cell array including a memory cell group having a plurality of memory cells, and a redundancy memory cell group having a plurality of redundancy memory cells, each of the plurality of memory cells having a retention time equal to or greater than a preset refresh period for the memory cell array; a test circuit that determines a retention time of each of the plurality of memory cells and the plurality of redundancy memory cells, and determines whether each of the plurality of memory cells satisfies a repair condition based on the determined retention time; and a repair circuit that repairs a first memory cell that has a minimum retention time among the plurality of memory cells using one of the plurality of redundancy memory cells, in response to the test circuit determining that the first memory cell satisfies a repair condition.