Memory Cell Repair Using Redundancy to Extend Refresh Period
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Solution Overview
Problem
Semiconductor memory cells may degrade due to defects or physical damage, necessitating a repair method that addresses performance degradation and unnecessary refresh operations in memory cell arrays.
Innovation Solution
A memory system with a redundancy memory cell group and repair circuit that identifies and repairs weak memory cells using redundancy cells, ensuring all cells meet a preset refresh period, thereby extending the refresh period and improving data bandwidth.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a refresh operation is performed for all memory cells, then data integrity is maintained, but unnecessary refresh operations increase time loss and reduce productivity
Solution Approach 1:
The patent applies local quality by differentiating memory cells into strong cells (with sufficient retention time) and weak cells (with insufficient retention time). The refresh operation is then selectively applied only to weak cells that require repair, rather than uniformly applying refresh to all cells. This localized approach maintains data integrity for cells that need it while avoiding unnecessary operations on cells that are already reliable.
Solution Approach 2:
The patent replaces the conventional mechanical refresh operation system with a test-based identification system. Instead of blindly performing refresh operations on all cells, the system uses a test circuit to measure retention times and identify weak cells, then applies repair operations only to those identified cells. This substitution of mechanical blind refresh with intelligent identification and selective repair reduces unnecessary time loss.
2Reliability
If memory cells with degraded performance are repaired, then reliability improves, but device complexity increases due to additional test and repair circuits
Solution Approach 1:
The patent applies universality by designing the test circuit to serve multiple functions: it not only identifies weak cells but also characterizes their retention time characteristics to determine repair priority. The repair circuit similarly handles multiple tasks including selecting appropriate redundancy cells, managing repair operations, and updating mapping information. This multi-functional approach consolidates complexity into unified circuits rather than requiring separate dedicated circuits for each function.
Solution Approach 2:
The patent uses copying by creating redundancy memory cells that are copies of the original memory cells. These redundancy cells serve as replacements for failed or degraded cells. The test circuit measures retention times of both original and redundancy cells, and the repair circuit uses these copies to replace weak cells, thereby maintaining reliability while managing complexity through standardized replacement units.
3Productivity
If the refresh period is extended, then productivity increases, but data integrity may be compromised for weak memory cells
Solution Approach 1:
The patent applies preliminary action by performing retention time testing and identifying weak cells before the extended refresh period begins. The system pre-characterizes the retention characteristics of all memory cells and marks weak cells for repair. This preliminary identification allows the system to extend the refresh period for strong cells while ensuring that weak cells are repaired in advance to maintain data integrity throughout the extended operation period.
Solution Approach 2:
The patent implements feedback by continuously monitoring retention times and using this information to adjust repair strategies. The test circuit measures retention times, and this feedback is used by the repair circuit to determine which cells need repair and when. This feedback loop ensures that the extended refresh period does not compromise data integrity, as the system adapts its repair operations based on real-time retention characteristics.
Data Source
AI summary
A memory system includes a memory cell array including a memory cell group having a plurality of memory cells, and a redundancy memory cell group having a plurality of redundancy memory cells, each of the plurality of memory cells having a retention time equal to or greater than a preset refresh period for the memory cell array; a test circuit that determines a retention time of each of the plurality of memory cells and the plurality of redundancy memory cells, and determines whether each of the plurality of memory cells satisfies a repair condition based on the determined retention time; and a repair circuit that repairs a first memory cell that has a minimum retention time among the plurality of memory cells using one of the plurality of redundancy memory cells, in response to the test circuit determining that the first memory cell satisfies a repair condition.