Semiconductor Memory Cell Repair via System Management Interrupt
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Solution Overview
Problem
Semiconductor memory devices face challenges in effectively repairing defective memory cells, which can cause read errors during operation, as existing error correction mechanisms have limitations in continuously correcting frequent errors.
Innovation Solution
A method involving a system management interrupt to invoke a basic input/output system service routine for repairing defective memory cells using spare memory cells, where defective cell information is checked and stored, and the repair is performed during the BIOS service routine execution, either during reboot or runtime, to restore memory cell functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an ECC engine is used to correct read errors, then some errors can be corrected, but there is a limitation in correction capability and frequent errors cannot be continuously corrected
Solution Approach 1:
The patent performs preliminary detection of defective memory cells during manufacturing or initial operation, and pre-configures spare memory cells to replace identified defective cells before they cause operational failures. This preliminary action enables continuous correction of frequent errors by having repair mechanisms ready in advance.
Solution Approach 2:
The patent introduces spare memory cells as intermediary elements that mediate between defective memory cells and the operational memory system. These spare cells act as a buffer, allowing the system to maintain functionality even when original cells fail, thereby enabling continuous operation and correction.
2Reliability
If defective memory cells are repaired using spare memory cells during operation, then read errors can be corrected, but system downtime or performance degradation may occur
Solution Approach 1:
The patent detects and identifies defective memory cells during manufacturing or initial system operation, before they cause critical failures. Spare memory cells are pre-configured and mapped to replace identified defective cells, allowing repairs to be performed without significant system downtime or performance degradation during normal operation.
Solution Approach 2:
The patent implements an automatic repair mechanism where the memory system self-diagnoses defective cells and self-repairs by activating pre-configured spare cells without requiring external intervention or significant system downtime. The system continuously monitors and automatically switches to spare cells when defects are detected, maintaining productivity during repair operations.
3Reliability
If memory cells are continuously monitored for errors, then defective cells can be detected early, but system complexity and overhead increase
Solution Approach 1:
The patent integrates error detection and repair functions into the existing memory controller and ECC engine, making these components multi-functional. The same hardware that manages normal memory operations also performs defect detection and spare cell activation, eliminating the need for separate monitoring systems and reducing overall complexity.
Solution Approach 2:
The memory system performs self-diagnosis and self-repair through integrated monitoring capabilities within the existing memory controller. The system automatically detects defective cells and activates spare cells without requiring external monitoring equipment, thereby detecting defects early while minimizing the increase in system complexity.
Data Source
AI summary
Provided is a method for repairing one or more defective memory cells of a semiconductor memory device by a system management interrupt and a basic input/output system service routine. In the method, when an error has occurred in data read from the semiconductor memory device, the system management interrupt is generated to invoke the basic input/output system service routine. During execution of the basic input/output system service routine, a repair task is performed to one or more defective memory cells causing a read error in the semiconductor memory device using spare memory cells.