Single Bit Memory Cell Reprogramming Without Block Erasure
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Solution Overview
Problem
High-density flash memory devices face inefficiencies due to large block sizes, requiring frequent block erases for single memory cell changes, which increases operational complexity and reduces endurance as the number of layers increases.
Innovation Solution
Implementing a one-erase, multiple-write programming method that allows incremental voltage adjustments in memory cells, enabling multiple write operations within a single bit per cell memory, reducing the need for block erase operations and improving endurance by allowing memory cells to be programmed multiple times within a full threshold voltage range.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If block erase operations are performed frequently to change programmed memory cells back to erased state, then memory cells can be reused, but operating speed decreases and endurance is reduced due to the large number of slow erase cycles
Solution Approach 1:
The patent segments the block erase operation into finer granularity by enabling individual cell or small group erasure. Instead of erasing entire large blocks, the system can target and erase only specific memory cells that need to be changed from programmed to erased state, dramatically reducing the number of erase cycles required and improving both speed and endurance.
Solution Approach 2:
The patent changes the operational parameters of memory cells by utilizing multiple threshold voltage ranges within a single cell. By programming cells to different voltage levels (e.g., first range for logic state A, second range for logic state B), the system can perform multiple write operations without requiring intermediate erases, thereby reducing erase cycle frequency and improving endurance.
2Quantity of substance
If block size is increased to achieve high density, then storage capacity increases, but the complexity and time required for erase operations increases
Solution Approach 1:
The patent divides the large block into smaller erasable units or enables selective erasure of individual cells within the block. This segmentation allows the system to maintain high storage capacity through large block size while performing much faster, smaller-scale erase operations on only the necessary portions, significantly reducing erase operation time.
Solution Approach 2:
The patent extracts the erase operation from the block level down to the cell or small group level. By taking out the erase function from the block-level operation and applying it at a finer granularity, the system can maintain high density blocks while performing rapid, targeted erasures that don't require processing the entire large block.
3Productivity
If multiple write operations are performed on the same memory cell, then data can be updated, but traditional single-bit cells require block erase between writes reducing efficiency
Solution Approach 1:
The patent applies parameter changes by utilizing multiple threshold voltage ranges within a single memory cell. Instead of treating each cell as a binary state requiring full erase between writes, the system programs cells to different voltage levels (first range, second range, etc.) to represent different data states, enabling multiple write operations without intermediate erases and significantly improving write efficiency.
Data Source
AI summary
A method to operate a single bit per cell memory comprises erasing a group of memory cells establishing a first logical value by setting threshold voltages in a first range of threshold voltages. First writing, after said erasing, includes programming first selected memory cells to establish a second logical value by setting threshold voltages in a second range of threshold voltages, and saving a sensing state parameter to indicate a first read voltage. Second writing, after said first writing, includes programming second selected memory cells to establish the second logical value by setting threshold voltages in a third range of threshold voltages, and saving the sensing state parameter to indicate a second read voltage. After a number of writings including said first writing and said second writing reaches a threshold number for writing the group of memory cells, the group of memory cells can be erased.