State-Monitoring Memory Cell for Low-Voltage Reset Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing voltage detector circuits in Integrated Circuits (ICs) consume high power and generate unnecessary reset signals due to their reliance on resistive voltage dividers, which are not sensitive enough to trigger resets at lower voltage thresholds, leading to potential IC damage.
Innovation Solution
Implementing a state-monitoring memory element with a reduced ability to retain logic states, coupled with a voltage supply circuit using diodes or transistors to degrade input voltage and current sources to stress the element, allowing for early detection of voltage drops and accurate failure indication, thus reducing power consumption and controlling reset triggers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a resistive voltage divider is used in the voltage detector circuit, then the voltage state can be monitored, but the power consumption increases due to constant current drainage
Solution Approach 1:
The patent extracts the monitoring function from the power supply path by using a separate sensing mechanism. The voltage detector circuit monitors voltage through a FET gate connection to the voltage divider output without drawing continuous current from the main power path, separating the monitoring function from the power consumption path.
Solution Approach 2:
The voltage divider circuit serves dual purposes: it provides voltage scaling for the FET gate control and simultaneously provides the monitor output signal. The same voltage division structure that controls the FET also feeds the monitoring function, eliminating the need for a separate monitoring circuit that would consume additional power.
2Reliability
If a voltage threshold is set to trigger reset signal, then IC damage can be prevented, but unnecessary reset signals occur due to insufficient sensitivity
Solution Approach 1:
The patent applies different quality requirements to different parts of the voltage detection system. The FET gate receives a scaled voltage for threshold comparison, while the monitor output receives the full-resolution voltage divider output. This allows the threshold triggering function and the monitoring function to operate with different precision requirements simultaneously.
Solution Approach 2:
The FET acts as an intermediary between the voltage divider output and the reset trigger. The FET gate voltage provides a threshold-based decision point, while the monitor output provides continuous voltage information. This intermediary structure allows the system to distinguish between genuine low-voltage conditions requiring reset and transient variations that should be monitored but not trigger reset.
3Reliability
If the voltage detector circuit uses a FET with voltage threshold control, then reset signal can be generated, but the circuit consumes high power due to the voltage divider
Solution Approach 1:
The voltage divider circuit performs multiple functions simultaneously: it provides voltage scaling for FET gate control, generates the monitor output signal, and enables threshold-based reset triggering. By making the voltage divider multi-functional, the patent eliminates the need for separate circuits that would increase power consumption.
Solution Approach 2:
The FET operates in a switching manner rather than continuous conduction. The FET is turned on when voltage threshold is exceeded and off when voltage is sufficient, creating a periodic or event-driven operation pattern rather than continuous power consumption. This switching action reduces average power consumption while maintaining reliable reset signal generation.
Data Source
AI summary
Embodiments of the invention relate to a state-monitoring memory element. The state-monitoring memory element may have a reduced ability to retain a logic state than other regular memory elements on an IC. Thus, if the state-monitoring memory elements fails or loses state during testing, it may be a good indicator that the IC's state retention may be in jeopardy, possibly requiring the IC to be reset. The state-monitoring memory element may be implemented by degrading an input voltage supply to the state-monitoring memory element across a diode and/or a transistor. One or more current sources may be used to stress the state-monitoring memory element. A logic analyzer may be used to analyze the integrity of the state-monitoring memory element and trigger appropriate actions in the IC, e.g., reset, halt, remove power, interrupt, responsive to detecting a failure in the state-monitoring memory element. Multiple state-monitoring memory elements may be distributed in different locations on the IC for better coverage.