Memory Cell Reset Ramped Current Pulse Scheme
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional memory systems face challenges in reliably programming non-volatile memory cells, particularly in transitioning between set and reset states due to drifting electrical characteristics over time, leading to reduced endurance and failure in maintaining sufficient current for reset operations.
Innovation Solution
Implementing a memory system with a controller and access circuitry that applies a minimal current initially to attempt programming, and subsequently increases the current if the cell fails to reset, using a ramped pulse scheme to extend endurance by avoiding excessive current usage and ensuring successful reset operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a high current is applied to reset the memory cell, then the reset operation succeeds, but the endurance of the memory cell deteriorates due to excessive current usage
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the current magnitude in a ramped sequence (e.g., from 100 µA to 200 µA to 300 µA) rather than using a fixed high current. This progressive parameter adjustment ensures the memory cell resets successfully while minimizing excessive current stress, thereby improving endurance without sacrificing reset reliability.
Solution Approach 2:
The patent implements dynamics by transitioning from a static high-current approach to a dynamic ramped pulse scheme where the current increases stepwise based on verification results. The controller adjusts the current level adaptively, applying higher current only when necessary and lower current when sufficient, thus optimizing both reset success and cell endurance over time.
2Duration of action of stationary object
If a minimal current is applied to the memory cell, then the endurance is extended, but the reset operation may fail
Solution Approach 1:
The patent uses dynamics to transition from a static minimal-current approach to a dynamic ramped pulse scheme. The current starts minimal to preserve endurance but increases progressively if verification fails, ensuring reset success is maintained while minimizing unnecessary high-current stress on successfully reset cells.
Solution Approach 2:
The patent applies feedback by using verification operations to determine whether the memory cell has successfully reset. Based on this feedback, the controller decides whether to continue with the current level or ramp up to a higher current level, creating a closed-loop control system that adapts to the actual cell state and ensures reliable reset while preserving endurance.
3Reliability
If subsequent reset pulses are applied with the same current until the memory cell places in the reset state, then the reset operation is completed, but the time and current consumption increase
Solution Approach 1:
The patent applies parameter changes by ramping up the current level in subsequent pulses (e.g., from 100 µA to 200 µA to 300 µA) rather than repeating the same current. This progressive parameter change accelerates the reset process for cells that fail initial attempts, reducing the total number of pulses needed and thereby decreasing programming time and current consumption.
Solution Approach 2:
The patent implements dynamics by making the current level adaptive rather than static. The controller dynamically adjusts the current magnitude based on verification outcomes, applying higher current only when and where needed, thus optimizing the balance between reset reliability and programming efficiency without unnecessary time or energy waste.
Data Source
AI summary
Memory systems and memory programming methods are described. According to one arrangement, a memory system includes a memory array comprising a plurality of memory cells individually configured to have a plurality of different memory states, access circuitry configured to apply signals to the memory cells to program the memory cells to the different memory states, and a controller to configured to control the access circuitry to apply a first of the signals to one of the memory cells to program the one memory cell from a first memory state to a second memory state different than the first memory state, to determine that the one memory cell failed to place into the second memory state as a result of the application of the first signal, and to control the access circuitry to apply a second signal to the one memory cell to program the one memory cell from the first memory state to the second memory state as a result of the determination, wherein the first and second signals have a different electrical characteristic.