Non-volatile Memory Cell Resistance State Detection Circuit
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Solution Overview
Problem
Conventional resistance change type memory devices require three steps for data writing/erasing (reading, writing, and erasing), leading to high processing time and power consumption.
Innovation Solution
A non-volatile semiconductor storage device with a data writing unit that includes a voltage supply circuit and resistance state detecting circuits, allowing for parallel execution of set and reset operations without the need for a read operation, thereby reducing processing time and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If data is written/erased in three steps (reading, writing, and erasing) in conventional resistance change type memory, then data can be accurately managed, but processing time and power consumption increase
Solution Approach 1:
The patent extracts the read operation from the data write/erase process. By using a voltage supply circuit that can detect resistance state changes during the write/erase operation itself, the separate read step is eliminated. The resistance state detecting circuit monitors the variable resistive element's state during voltage application, allowing the system to determine when writing/erasing is complete without performing a separate read operation.
Solution Approach 2:
The patent enables continuous useful action by performing data writing/erasing and state detection simultaneously in a single operation. The voltage supply circuit continuously applies voltage to change the resistance state while the resistance state detecting circuit continuously monitors the process, eliminating idle time between separate read, write, and erase operations.
2Reliability
If data is written/erased in three steps (reading, writing, and erasing) in conventional resistance change type memory, then data can be accurately managed, but power consumption increases
Solution Approach 1:
The patent extracts the read operation from the data write/erase process. By using a voltage supply circuit that can detect resistance state changes during the write/erase operation itself, the separate read step is eliminated. The resistance state detecting circuit monitors the variable resistive element's state during voltage application, allowing the system to determine when writing/erasing is complete without performing a separate read operation.
Solution Approach 2:
The patent merges the write/erase operation with the state detection operation into a single integrated process. The voltage supply circuit and resistance state detecting circuit work simultaneously during one operation cycle, combining what were previously separate read, write, and erase steps into a unified operation that consumes less power.
3Area of stationary object
If a serial circuit of Schottky diode and variable resistive element is used in memory cell, then high degree of integration is achieved, but processing complexity increases
Solution Approach 1:
The patent makes the voltage supply circuit multi-functional by enabling it to perform both data writing/erasing and resistance state detection. This single circuit structure handles multiple operations that would otherwise require separate circuits, simplifying the overall device architecture while maintaining high integration density achieved by the serial Schottky diode and variable resistive element configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables faster data write operations and reduced power consumption by eliminating the need for a read operation before writing, thereby improving efficiency in data management.
Implementation Method 1
a variable resistive element that changes a resistance value by application of an electric pulse
Data Source
AI summary
A non-volatile semiconductor storage device includes a memory cell array having plural electrically rewritable memory cells, each memory cell including a variable resistive element storing resistance values as data in a non-volatile manner, and a data writing unit having a voltage supply circuit which supplies a voltage needed to write data to the plural memory cells, and a resistance state detecting circuit which detects a resistance state of the variable resistive element at the time of writing the data. The data writing unit stops the supply of the voltage to the memory cell where a resistance state of the variable resistive element becomes a desired resistance state, among the plural memory cells, according to the detection result of the resistance state detecting circuit.