Semiconductor Memory Cell Doped Region Resistor Current Limiting

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Solution Overview

Problem

Semiconductor memory devices face issues with excessive current flow between the capacitor and transistor during programming, leading to potential transistor damage and accuracy problems due to unregulated voltage differences.

Innovation Solution

Incorporating a doped region resistor between the capacitor and transistor, which acts as a voltage regulator, reducing current flow and allowing for flexible capacitor size adjustments, thereby enhancing manufacturing process flexibility and device quality.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If a direct connection is made between the capacitor and transistor, then the programming operation is simple, but excessive current flows causing transistor damage

Engineering Contradiction:
Improveprogramming operation simplicityVSAvoidtransistor protection
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

A doped region resistor is introduced as an intermediary component between the capacitor and transistor. This resistor limits the current flowing from the capacitor to the transistor during programming operations, preventing transistor damage while maintaining process simplicity. The resistor is formed through standard doping processes integrated into the existing memory cell fabrication flow.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Area of stationary object

If the capacitor size is reduced to improve device integration, then the memory density increases, but the voltage regulation capability deteriorates

Engineering Contradiction:
Improvecapacitor areaVSAvoidvoltage regulation capability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The voltage regulation function is segmented from the capacitor structure and implemented through a separate doped region resistor. This allows the capacitor to be miniimized for high density while the resistor provides the necessary voltage regulation. The segmentation enables independent optimization of capacitor size and resistance value to meet both density and reliability requirements.

Inventive Principle:
Principle #1Segmentation

3Reliability

If a doped region resistor is added between the capacitor and transistor, then the transistor is protected from excessive current, but the device complexity increases

Engineering Contradiction:
Improvetransistor protectionVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The doped region resistor is merged with the existing capacitor structure by using the same doped region that forms the capacitor bottom electrode. This integration means no additional processing steps are required beyond standard doping operations, and the resistor shares physical space with the capacitor structure, minimizing the increase in device complexity while providing necessary current limiting protection.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The resistor effectively mitigates excessive current flow, protects the transistor, and allows for flexible capacitor sizing, improving the semiconductor memory device's performance and manufacturing process.

Implementation Method 1

the resistor can effectively reduce the voltage difference between the capacitor and the transistor, and prevent excessive current from flowing into transistor

Methodology Applied
Scientific EffectElectrical Resistance: Electrical Resistance

Data Source

PatentUS20220302118A1Semiconductor memory cell and the forming method thereof
Publication Date: 2022.09.22 UNITED MICROELECTRONICS CORP
  • US20220302118A1 patent drawing
  • US20220302118A1 patent drawing

AI summary

The invention provides a semiconductor memory cell, the semiconductor memory cell includes a substrate having a first conductivity type, a doped region in the substrate, wherein the doped region has a second conductivity type, and the first conductivity type is complementary to the second conductivity type, a capacitor insulating layer and an upper electrode on the doped region, a transistor on the substrate, and a shallow trench isolation disposed between the transistor and the capacitor insulating layer, and the shallow trench isolation is disposed in the doped region.