Memory-Cell Random Number Generation for Secure Bus Encryption
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Solution Overview
Problem
Existing pseudo-random number generators for bus encryption have security vulnerabilities due to low linear complexity and high hardware requirements, leading to inefficiencies in chip area usage and increased costs, as they rely on a single key sequence for multiple bus lines, making them susceptible to cryptographic attacks.
Innovation Solution
A random number generator with a series of memory cells and feedback means that combines states of groups of memory cells to generate distinct output sequences for each bus line, using non-linear feedback shift registers to produce maximally periodic sequences with high linear complexity, thereby reducing hardware requirements and enhancing security.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a linear feedback shift register is used to generate pseudo-random sequences, then the hardware complexity is very low, but the linear complexity is also low making it vulnerable to cryptographic attacks
Solution Approach 1:
The patent combines multiple LFSR sequences by selecting and combining outputs from different memory cells of multiple LFSRs. This merging approach maintains the low hardware complexity of individual LFSRs while achieving high linear complexity through the combination of multiple sequences, thereby resolving the contradiction between hardware simplicity and security.
Solution Approach 2:
The patent creates a composite pseudo-random sequence by combining outputs from multiple LFSRs with different characteristic polynomials. This composite approach uses the strengths of multiple simpler components to achieve the security properties of a complex system while maintaining low hardware complexity.
2Reliability
If multiple memory cells are used to increase the period duration, then the security is improved, but the chip area increases leading to higher costs
Solution Approach 1:
The patent makes a single pool of memory cells serve multiple functions by allowing different combinations of these cells to generate sequences for multiple bus lines. This multi-functionality approach increases security through sequence diversity while avoiding the need to allocate separate memory cells for each bus line, thereby controlling chip area.
Solution Approach 2:
The patent changes the parameters of sequence generation by using different characteristic polynomials and different combinations of memory cell outputs. This allows the same hardware resources to produce multiple distinct sequences with different properties, achieving high security without proportionally increasing chip area.
3Area of stationary object
If the same key sequence is used for multiple bus lines, then the chip area is reduced, but the security is compromised as attackers can derive other sequences through time-shifting
Solution Approach 1:
The patent segments the single key sequence into multiple distinct sequences by selecting different combinations of memory cell outputs for different bus lines. This segmentation ensures that each bus line receives a unique sequence that cannot be derived from others through time-shifting, maintaining security while using the same underlying hardware resources.
Solution Approach 2:
The patent introduces a new dimension of sequence differentiation by using different characteristic polynomials and different memory cell combinations, rather than relying solely on time-shifting. This dimensional change in sequence generation ensures that sequences for different bus lines are fundamentally distinct and cannot be derived from one another.
Data Source
AI summary
A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.