Memory Cell Segmentation for High-Speed Writing and Low Power
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing storage devices using MTJ elements face challenges in achieving high-speed writing while minimizing current usage during standby, leading to increased power consumption and larger occupied areas due to the need for high currents and complex data backup/loading processes.
Innovation Solution
A storage device with a memory cell comprising a first storage circuit for high-speed writing and a second storage circuit for data retention, where the write data is supplied over a specific time frame and power is controlled to optimize writing and retention times, allowing for parallel data writing and extended retention without prolonged power supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high current is applied to MTJ elements for high-speed writing, then writing speed is improved, but power consumption increases
Solution Approach 1:
The storage device is divided into two independent storage circuits (first storage circuit with fast write time and second storage circuit with long retention time) that operate in parallel. This segmentation allows each circuit to be optimized for its specific function, enabling high-speed writing without requiring prolonged high current application, thus reducing overall power consumption.
2Reliability
If data backup and loading processes are implemented using MTJ elements, then data retention during power-off is improved, but device complexity increases
Solution Approach 1:
The patent combines volatile and nonvolatile storage functions into a unified memory cell structure where the first and second storage circuits share common bit lines and control logic. This merging eliminates the need for separate backup and loading circuits, reducing device complexity while maintaining data retention reliability.
Solution Approach 2:
The second storage circuit using MTJ elements serves multiple functions: it acts as both a nonvolatile backup storage during power-off and a functional storage element during power-on operations. This multi-functionality eliminates the need for dedicated backup circuits, simplifying the overall device structure.
3Reliability
If writing time is extended to match MTJ switching time, then writing reliability is improved, but productivity decreases
Solution Approach 1:
The storage system is segmented into two parallel storage circuits with different characteristic times. The first storage circuit completes writing quickly for high throughput, while the second storage circuit ensures reliability with longer retention. This segmentation allows the system to achieve both high productivity and writing reliability simultaneously.
Solution Approach 2:
The patent applies partial action by writing data to only the first storage circuit when speed is critical, and engages the second storage circuit only when retention reliability is required. This selective engagement optimizes the balance between productivity and reliability based on operational needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables a compact storage device capable of high-speed writing with minimal current usage during standby, reducing power consumption and occupied area by optimizing the write and retention times of the storage circuits.
Implementation Method 1
a resistance-change-type storage element with a write time t2 and a data retention time τ2
Data Source
AI summary
A memory cell (1) includes a first storage circuit (2) with a write time t1 and a data retention time τ1 and a second storage circuit (3) with a write time t2 and a data retention time τ2 (t1<t2 and τ1<τ2). A row decoder supplies write data to the memory cell (1) via a word line (WL) to write the data on the first storage circuit (2) over a write time tW that is longer than the write time t1 and that is shorter than the write time t2. A PL control circuit (4) supplies power to the memory cell (1) for a time that is longer than the write time t2 when the write data is supplied to the memory cell (1), writes, on the second storage circuit (3), the data written on the first storage circuit (2) once the supply of the write data is stopped, and stops the supply of the power to the memory cell (1) after a lapse of the write time t2 following start of the supply of the write data.