Low Power Radiation Hardened Memory Cell Using Segmented Nodes
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Solution Overview
Problem
Existing memory cells face increased susceptibility to radiation-induced errors and high power consumption due to scaling in the microelectronics industry, with low voltage operation exacerbating radiation susceptibility and failing to combine low power and Single Event Upset (SEU) tolerance effectively.
Innovation Solution
The design incorporates a pair of cross-coupled gated inverters with cut-off networks to create redundant data storage nodes, allowing for electrical separation and restoration of corrupted data, and high resistance supply rail connections to reduce leakage currents and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If transistor dimensions are scaled down, then device density increases, but susceptibility to radiation-induced errors increases
Solution Approach 1:
The memory cell is divided into two separate data storage nodes (Q1 and Q2) that are electrically isolated from each other using cut-off networks. This segmentation allows the cell to maintain high density while reducing radiation susceptibility, as a radiation strike affecting one node can be detected and corrected using the other node as reference, preventing single event upsets from corrupting stored data.
Solution Approach 2:
The invention changes the electrical parameters of the supply rail connections by introducing high resistance connections (using resistors or deliberately designed high-resistance paths) between the power supply and the memory cell circuits. This parameter change reduces the current available for radiation-induced charge collection, thereby lowering susceptibility to radiation errors while maintaining functional operation.
2Use of energy by stationary object
If low voltage operation is implemented, then power consumption decreases, but radiation susceptibility increases
Solution Approach 1:
By segmenting the storage into two nodes and implementing continuous monitoring through the cut-off network architecture, the system can operate at low voltages while maintaining radiation hardness. The segmented structure allows for error detection and correction mechanisms that compensate for the reduced noise margin inherent in low-voltage operation, thus reducing radiation susceptibility without sacrificing power efficiency.
Solution Approach 2:
The dual-node architecture with cut-off networks provides a form of beforehand cushioning by preparing redundant storage paths and monitoring mechanisms in advance. When operating at low voltages where radiation strikes are more likely to cause upsets, this pre-configured redundancy acts as a protective buffer, allowing the system to tolerate and correct radiation-induced errors that would otherwise be catastrophic in single-node low-voltage designs.
3Reliability
If redundant data storage nodes are created, then SEU tolerance improves, but device complexity increases
Solution Approach 1:
The memory cell is segmented into two storage nodes with cut-off networks that can be independently controlled. This segmentation enables SEU tolerance through error detection and correction capabilities while managing complexity through modular design. The cut-off networks act as simple switching elements that can be integrated into existing CMOS processes, adding functionality without proportionally increasing overall device complexity.
Solution Approach 2:
The dual-node architecture with cut-off networks serves multiple functions simultaneously: it provides data storage, error detection, error correction, and radiation hardening all within a single cell structure. This multi-functionality improves SEU tolerance without linearly increasing complexity, as the same structural elements serve multiple protective and operational roles rather than requiring separate dedicated circuits for each function.
4Loss of energy
If high resistance supply rail connections are implemented, then leakage currents decrease, but voltage drop increases
Solution Approach 1:
The supply rail connections use high resistance paths that are optimized to provide sufficient current during active operation while minimizing leakage during standby. The resistance values are carefully selected to balance the trade-off between leakage reduction and voltage drop, ensuring that the memory cell maintains adequate voltage levels for reliable operation while achieving significant leakage current reduction for low-power operation.
Solution Approach 2:
The high resistance supply rail connections are配合 with periodic refresh operations where the cut-off networks are temporarily opened to recharge the storage nodes from the supply rails. This periodic action allows the system to use high resistance connections for leakage reduction during normal operation while periodically replenishing charge to compensate for the higher voltage drop, achieving both low leakage and adequate voltage levels through time-multiplexed operation.
Data Source
AI summary
The invention concerns a memory cell having: first and second cross-coupled gated inverters (102, 104), each including first and second inputs (IN1, IN2) and an output (OUT) and being adapted to couple its output to a first logic level only when the first and second inputs both receive the inverse of the first logic level; a first cut-off circuit (106) coupling the second input (IN2) of the first gated inverter (102) to the first input (IN1) of the first gated inverter (102); and a second cut-off circuit (108) coupling the second input (IN2) of the second gated inverter (104) to the first input (IN1) of the second gated inverter (104).