High Aspect Ratio Memory Cell Layout for SEU Tolerance
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Solution Overview
Problem
CMOS memory cells face challenges in providing single event upset (SEU) tolerance as design technology decreases, leading to inadequate spacing between redundant nodes, which increases the likelihood of data corruption from ion hits, especially in smaller geometry IC designs.
Innovation Solution
A memory cell layout with a high aspect ratio of at least 5:1 is implemented, featuring separated N-wells and P-wells with strategically placed P-taps and N-taps to physically and electrically isolate redundant nodes, ensuring that a single ion hit is unlikely to alter both data values, thus maintaining data integrity even in smaller technology designs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If standard CMOS memory cell layout is used, then manufacturing is simple and area is small, but spacing between redundant nodes is insufficient leading to SEU vulnerability
Solution Approach 1:
The memory cell layout transitions from a conventional square-like arrangement to a high aspect ratio configuration (at least 5:1), effectively utilizing the vertical dimension to separate redundant nodes. This dimensional change allows sufficient spacing between nodes Q and QQ, Qb and QQb to prevent simultaneous ion hits while maintaining compact footprint through optimized vertical stacking of transistor components.
Solution Approach 2:
The memory cell is segmented into distinct functional regions with N-wells and P-wells strategically separated. The layout divides the cell into left and right sides with storage nodes Q and QQ on one side, and Qb and QQb on the other, ensuring physical separation of redundant node pairs. This segmentation allows independent protection of each node pair against ion-induced upsets.
2Productivity
If design technology decreases to achieve smaller ICs, then device size reduces and integration increases, but spacing between redundant nodes becomes inadequate increasing ion hit vulnerability
Solution Approach 1:
The invention changes the geometric parameters of the memory cell layout by enforcing a minimum aspect ratio of 5:1, which fundamentally alters the spatial distribution of components. This parameter change ensures that even as overall device dimensions scale down with smaller technology nodes, the critical spacing between redundant nodes Q-QQ and Qb-QQb maintains adequate separation distance to withstand ion hits, thus preserving SEU tolerance alongside integration density improvements.
3Ease of manufacture
If N-wells and P-wells are closely spaced to reduce area, then manufacturing efficiency increases, but electrical isolation between redundant nodes decreases leading to data corruption
Solution Approach 1:
The layout introduces intermediate structures including P-taps and N-taps that act as electrical mediators and isolation barriers between N-wells and P-wells. These intermediate elements provide controlled electrical connection points while maintaining physical separation, ensuring that redundant nodes remain electrically isolated to prevent simultaneous upset while allowing efficient fabrication through standardized tap structures.
Data Source
AI summary
A memory cell having a plurality of transistors connected so as to restore a data value to a node of the memory cell to an initial value following an event upsetting the initial value has an aspect ratio of at least 5:1. The high aspect ratio provides adequate spacing between nodes of the memory cell for SEU tolerance at small design technologies.